Abstract: Disclosed are a method and apparatus for processing and uploading a video file The method of processing the video file comprises: providing an image editor comprising an integrated user interface, which comprises a preview monitor and an editing board, wherein a plurality of thumbnail images of a plurality of videos are displayed on the editing board; displaying a selected one of the plurality of videos or a still frame of the selected video on the preview monitor in response to a user's selection of the video and the user's command for playing the selected video; and editing the selected video so as to provide an edited version of the selected video in response to the user's editing command while or after displaying the selected video on the preview monitor.

Abstract: An apparatus for dispensing liquid crystal material including a container containing liquid crystal material, a discharge pump drawing-in liquid crystal material and discharging the drawn liquid crystal material, a nozzle dispensing the discharged liquid crystal material onto LCD panel regions as a plurality of liquid crystal droplets, and a control unit calculating a total amount of liquid crystal material to be dispensed onto each LCD panel region as a dispensing pattern of liquid crystal droplets each having an amount of liquid crystal material contained therein and for compensating the total amount of liquid crystal material by at least one of: compensating the predetermined number of liquid crystal droplets arranged within the predetermined dispensing pattern, and compensating the predetermined amount of liquid crystal material within at least one liquid crystal droplet.

Abstract: Digital broadcasting receiver, and method for compensating a color reproduction error therein, the digital broadcasting receiver including a channel decoder, a TP part for demultiplexing a TP stream from the channel decoder for being provided with a PCR (Program Clock Reference), and receiving a receiver side STC (System Time Clock), and providing a PCR jitter which is a difference between the PCR and an STC value, an STC compensating part for providing the STC value to the TP part from a system clock, and varying the system clock so that the PCR value and the STC value are identical, to generate a reference system clock in which the PCR jitter value becomes ‘0’, a decoder for receiving the reference system clock from the STC compensating part, and decoding a received picture, a display clock generator for providing a display clock generated by receiving the reference system clock as singular system clock, a video format and display processor for receiving the reference system clock and the display clock, and

Abstract: A flash memory device is disclosed that includes a control circuit for generating a count-up pulse signal notifying a generation of an address required for a burst read operation. An address generator circuit generates an address in response to the count-up pulse signal, and a discharge circuit discharges global bit lines in response to the count-up pulse signal. According to this control scheme, the global bit lines may be discharged before the local and global bit lines are selected.

Abstract: We describe a multi level flash memory device and program method. The multi level flash memory device includes a plurality of memory cells, each storing an amount of charge indicative of more than two possible states and control circuitry coupled to the memory cells. The control circuitry to applying a programming voltage alternating with a verification voltage to the memory cells until all are at a desired state and applying at least one additional programming voltage to the cells in a highest state without applying a verification voltage. The method includes applying at least one programming pulse to the cells, verifying that each cell has reached the desired state, selecting the cells that are programmed for a highest state, and applying at least one additional programming pulse to the selected cells without further verifying their state.

Abstract: A NOR-type flash memory device includes a global decoder circuit that is coupled to global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to local wordlines in each operation mode, and has wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select signal, and a sector generates a control signal in accordance with address information for selecting a memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordline. The depletion MOS transistors are commonly controlled by a control signal. Each of the wordline select switches is made of two NMOS transistors.

Abstract: Provided is a programming method of a flash memory device.

Abstract: We describe a multi level flash memory device and program method. The multi level flash memory device includes a plurality of memory cells, each storing an amount of charge indicative of more than two possible states and control circuitry coupled to the memory cells. The control circuitry to applying a programming voltage alternating with a verification voltage to the memory cells until all are at a desired state and applying at least one additional programming voltage to the cells in a highest state without applying a verification voltage. The method includes applying at least one programming pulse to the cells, verifying that each cell has reached the desired state, selecting the cells that are programmed for a highest state, and applying at least one additional programming pulse to the selected cells without further verifying their state.

Abstract: Provided is a programming method of a flash memory device.

Abstract: An apparatus for dispensing liquid crystal material including a container containing liquid crystal material, a discharge pump drawing-in liquid crystal material and discharging the drawn liquid crystal material, a nozzle dispensing the discharged liquid crystal material onto LCD panel regions as a plurality of liquid crystal droplets, and a control unit calculating a total amount of liquid crystal material to be dispensed onto each LCD panel region as a dispensing pattern of liquid crystal droplets each having an amount of liquid crystal material contained therein and for compensating the total amount of liquid crystal material by at least one of: compensating the predetermined number of liquid crystal droplets arranged within the predetermined dispensing pattern, and compensating the predetermined amount of liquid crystal material within at least one liquid crystal droplet.

Abstract: Is disclosed a flash memory device that includes a control circuit for generating a count-up pulse signal notifying a generation of an address required for a burst read operation. An address generator circuit generates an address in response to the count-up pulse signal, and a discharge circuit discharges global bit lines in response to the count-up pulse signal. According to this control scheme, the global bit lines may be discharged before the local and global bit lines are selected.

Abstract: A NOR-type flash memory device includes a global decoder circuit that is coupled to global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to local wordlines in each operation mode, and has wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select signal, and a sector generates a control signal in accordance with address information for selecting a memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordline. The depletion MOS transistors are commonly controlled by a control signal. Each of the wordline select switches is made of two NMOS transistors.

Abstract: A NOR-type flash memory device includes a global decoder circuit that is coupled to global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to local wordlines in each operation mode, and has wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select signal, and a sector generates a control signal in accordance with address information for selecting a memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordline. The depletion MOS transistors are commonly controlled by a control signal. Each of the wordline select switches is made of two NMOS transistors.

Abstract: An apparatus for generating a sync of a digital television in which an analog signal inputted to a digital television constantly provides stabilized synchronization regardless of a standard or a nonstandard so as to be processed.

Abstract: Digital broadcasting receiver, and method for compensating a color reproduction error therein, the digital broadcasting receiver including a channel decoder, a TP part for demultiplexing a TP stream from the channel decoder for being provided with a PCR (Program Clock Reference), and receiving a receiver side STC (System Time Clock), and providing a PCR jitter which is a difference between the PCR and an STC value, an STC compensating part for providing the STC value to the TP part from a system clock, and varying the system clock so that the PCR value and the STC value are identical, to generate a reference system clock in which the PCR jitter value becomes ‘0’, a decoder for receiving the reference system clock from the STC compensating part, and decoding a received picture, a display clock generator for providing a display clock generated by receiving the reference system clock as singular system clock, a video format and display processor for receiving the reference system clock and the displa

Abstract: A video processing method and apparatus for displaying a signal input in an analog form in a digital TV is disclosed. The present invention eliminates an interference between signals by unifying a flow of analog video signals having different formats, and several signal formats are processed without change through a basic construction of the hardware. Also, the efficiency is increased by utilizing an ADC, a clock and a clamp pulse generation in common for signals based on different formats. Furthermore, a stable interface operation is executed by reconstructing a horizontal synchronization with a constant width in a clock base, and performing a combination and a separation of digital signals on the basis of such construction.

Abstract: A NOR-type flash memory device includes a global decoder circuit that is coupled to global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to local wordlines in each operation mode, and has wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select signal, and a sector generates a control signal in accordance with address information for selecting a memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordline. The depletion MOS transistors are commonly controlled by a control signal. Each of the wordline select switches is made of two NMOS transistors.

Abstract: A NOR-type flash memory device includes a global decoder circuit that is coupled to global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to local wordlines in each operation mode, and has wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select signal, and a sector generates a control signal in accordance with address information for selecting a memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordline. The depletion MOS transistors are commonly controlled by a control signal. Each of the wordline select switches is made of two NMOS transistors.

Abstract: A non-volatile memory device of the present invention comprises a memory cell array having a plurality of cells, a plurality of dummy bit lines, a plurality of dummy word lines. At least one of the dummy bit lines includes a bulk tapping for applying bulk voltage. Here, P.sup.+ impurity is implanted into the dummy bit lines. With this improved memory structure, a device layout area can be reduced and an increase in bulk voltage resulting from hot carriers can be suppressed.

Abstract: A steering wheel having a collapsible hub, the steering wheel comprising a wheel 100 having a rim 140, a plurality of spokes 130 connected with the rim 140 and a lower plate 150 having edges and connected with the spokes 130 at the middle of the wheel 100, the edges of the lower plate forming a shape of an open box; a back plate 200 fixed to the said plurality of spokes 130 of the wheel 100 and having an escape hole 220 opened from the middle to one side of the plate 200; an upper plate 300 having first and second vertical surfaces 320 and 330 fixed to the back plate 200 and a horizontal surface 340 connecting the vertical surfaces 320 and 330 to form a space between the back plate 200 and the upper plate 300; and a hub cover 400 installed on the wheel 100 for covering the upper plate 300, so the upper plate 300 collapses to absorb impact of a driver in a car accident.