Patents by Inventor Dong-Hoon KHANG
Dong-Hoon KHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210272815Abstract: A method of fabricating a semiconductor device is provided. The method includes: forming mask patterns on a substrate, the mask patterns including a first mask fin pattern, a second mask fin pattern and a dummy mask pattern between the first mask fin pattern and the second mask fin pattern; forming a first fin pattern, a second fin pattern and a dummy fin pattern by etching the substrate using the mask patterns; and removing the dummy fin pattern, wherein the dummy mask pattern is wider than each of the first mask fin pattern and the second mask fin pattern.Type: ApplicationFiled: May 19, 2021Publication date: September 2, 2021Inventors: Chong Kwang Chang, Dong Hoon Khang, Sug Hyun Sung, Min Hwan Jeon
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Patent number: 11024509Abstract: A method of fabricating a semiconductor device is provided. The method includes: forming mask patterns on a substrate, the mask patterns including a first mask fin pattern, a second mask fin pattern and a dummy mask pattern between the first mask fin pattern and the second mask fin pattern; forming a first fin pattern, a second fin pattern and a dummy fin pattern by etching the substrate using the mask patterns; and removing the dummy fin pattern, wherein the dummy mask pattern is wider than each of the first mask fin pattern and the second mask fin pattern.Type: GrantFiled: August 14, 2019Date of Patent: June 1, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Chong Kwang Chang, Dong Hoon Khang, Sug Hyun Sung, Min Hwan Jeon
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Patent number: 10755932Abstract: To manufacture an integrated circuit device, a diffusion buffer layer and a carbon-containing layer are sequentially formed on a plurality of fin-type active regions formed in a substrate. A carbon-containing mask pattern is formed to have an opening exposing a portion of the diffusion buffer layer by etching the carbon-containing layer using an etching gas including an oxygen atom while the diffusion buffer layer is blocking oxygen from diffusing into the fin-type active regions. Impurity ions are implanted into some fin-type active regions through the opening and the diffusion buffer layer using the carbon-containing mask pattern as an ion-implantation mask, the some fin-type active regions being selected from among the plurality of fin-type active regions.Type: GrantFiled: July 17, 2018Date of Patent: August 25, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-woo Kang, Ji-ho Yoo, Dong-hoon Khang, Seon-bae Kim, Moon-han Park
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Publication number: 20200234966Abstract: A method of fabricating a semiconductor device is provided. The method includes: forming mask patterns on a substrate, the mask patterns including a first mask fin pattern, a second mask fin pattern and a dummy mask pattern between the first mask fin pattern and the second mask fin pattern; forming a first fin pattern, a second fin pattern and a dummy fin pattern by etching the substrate using the mask patterns; and removing the dummy fin pattern, wherein the dummy mask pattern is wider than each of the first mask fin pattern and the second mask fin pattern.Type: ApplicationFiled: August 14, 2019Publication date: July 23, 2020Inventors: Chong Kwang Chang, Dong Hoon KHANG, Sug Hyun SUNG, Min Hwan JEON
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Patent number: 10629604Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.Type: GrantFiled: March 12, 2019Date of Patent: April 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keun-hee Bai, Myeong-cheol Kim, Kwan-heum Lee, Do-hyoung Kim, Jin-wook Lee, Seung-mo Ha, Dong-Hoon Khang
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Patent number: 10622256Abstract: A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a first pattern on the sacrificial layer of the second region, forming a second pattern on the sacrificial layer of the first region, forming first upper spacers on opposite sidewalls of the second pattern, removing the second pattern, etching the first sacrificial layer of the first region using the first upper spacers as an etch mask to form a third pattern, etching the first sacrificial layer of the second region using the first pattern as an etch mask to form a fourth pattern, forming first lower spacers at either side of the third pattern, forming second spacers on opposite sidewalls of the fourth pattern, removing the third pattern and the fourth pattern, and etching the substrate using the first lower spacers and the second spacers as etch masks.Type: GrantFiled: March 28, 2016Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Jin Mun, Dong-Hoon Khang, Woo-Ram Kim, Cheol Kim, Dong-Seok Lee, Yong-Joon Choi, Seung-Mo Ha, Do-Hyoung Kim
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Publication number: 20190214394Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.Type: ApplicationFiled: March 12, 2019Publication date: July 11, 2019Inventors: Keun-hee BAI, Myeong-cheol KIM, Kwan-heum LEE, Do-hyoung KIM, Jin-wook LEE, Seung-mo HA, Dong-Hoon KHANG
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Patent number: 10304840Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.Type: GrantFiled: March 30, 2016Date of Patent: May 28, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keun-hee Bai, Myeong-cheol Kim, Kwan-heum Lee, Do-hyoung Kim, Jin-wook Lee, Seung-mo Ha, Dong-Hoon Khang
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Publication number: 20190139771Abstract: To manufacture an integrated circuit device, a diffusion buffer layer and a carbon-containing layer are sequentially formed on a plurality of fin-type active regions formed in a substrate. A carbon-containing mask pattern is formed to have an opening exposing a portion of the diffusion buffer layer by etching the carbon-containing layer using an etching gas including an oxygen atom while the diffusion buffer layer is blocking oxygen from diffusing into the fin-type active regions. Impurity ions are implanted into some fin-type active regions through the opening and the diffusion buffer layer using the carbon-containing mask pattern as an ion-implantation mask, the some fin-type active regions being selected from among the plurality of fin-type active regions.Type: ApplicationFiled: July 17, 2018Publication date: May 9, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-woo Kang, Ji-ho Yoo, Dong-hoon Khang, Seon-bae Kim, Moon-han Park
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Patent number: 10224204Abstract: An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern.Type: GrantFiled: February 8, 2018Date of Patent: March 5, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Hoon Khang, Dong-Woo Kang, Moon-Han Park, Ji-Ho Yoo, Chong-Kwang Chang
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Publication number: 20190051526Abstract: An integrated circuit device is manufactured by a method including forming a stacked mask structure including a carbon-containing film and a silicon-containing organic anti-reflective film is on a substrate, forming a silicon-containing organic anti-reflective pattern by etching the silicon-containing organic anti-reflective film, and forming a composite mask pattern including a carbon-containing mask pattern and a profile control liner lining interior surfaces of the carbon-containing mask pattern by etching the carbon-containing film while using the silicon-containing organic anti-reflective pattern as an etch mask. Ions are implanted into the substrate through a plurality of spaces defined by the composite mask pattern.Type: ApplicationFiled: February 8, 2018Publication date: February 14, 2019Inventors: DONG-HOON KHANG, DONG-WOO KANG, MOON-HAN PARK, JI-HO YOO, CHONG-KWANG CHANG
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Patent number: 9972538Abstract: Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.Type: GrantFiled: June 29, 2016Date of Patent: May 15, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Cheol Kim, Dong-Hoon Khang, Do-Hyoung Kim, Seung-Jin Mun, Yong-Joon Choi, Seung-Mo Ha
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Patent number: 9966375Abstract: A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.Type: GrantFiled: February 22, 2016Date of Patent: May 8, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Joon Choi, Tae-Yong Kwon, Mirco Cantoro, Chang-Jae Yang, Dong-Hoon Khang, Woo-Ram Kim, Cheol Kim, Seung-Jin Mun, Seung-Mo Ha, Do-Hyoung Kim, Seong-Ju Kim, So-Ra You, Woong-ki Hong
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Publication number: 20170040221Abstract: Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.Type: ApplicationFiled: June 29, 2016Publication date: February 9, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Cheol KIM, Dong-Hoon KHANG, Do-Hyoung KIM, Seung-Jin MUN, Yong-Joon CHOI, Seung-Mo HA
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Patent number: 9543155Abstract: A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.Type: GrantFiled: December 21, 2015Date of Patent: January 10, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Bok-Young Lee, Yoo-Jung Lee, Dong-Hoon Khang, Do-Hyoung Kim, Cheol Kim, In-Hee Lee, Ji-Eun Han
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Publication number: 20160358925Abstract: A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.Type: ApplicationFiled: March 30, 2016Publication date: December 8, 2016Inventors: Keun-hee BAI, Myeong-cheol KIM, Kwan-heum LEE, Do-hyoung KIM, Jin-wook LEE, Seung-mo HA, Dong-Hoon KHANG
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Publication number: 20160315085Abstract: A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.Type: ApplicationFiled: February 22, 2016Publication date: October 27, 2016Inventors: Yong-Joon CHOI, Tae-Yong KWON, Mirco CANTORO, Chang-Jae YANG, Dong-Hoon KHANG, Woo-Ram KIM, Cheol KIM, Seung-Jin MUN, Seung-Mo HA, Do-Hyoung KIM, Seong-Ju KIM, So-Ra YOU, Woong-ki HONG
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Publication number: 20160307803Abstract: A method of manufacturing a semiconductor device may include forming a sacrificial layer on a substrate including a first region and a second region, forming a first pattern on the sacrificial layer of the second region, forming a second pattern on the sacrificial layer of the first region, forming first upper spacers on opposite sidewalls of the second pattern, removing the second pattern, etching the first sacrificial layer of the first region using the first upper spacers as an etch mask to form a third pattern, etching the first sacrificial layer of the second region using the first pattern as an etch mask to form a fourth pattern, forming first lower spacers at either side of the third pattern, forming second spacers on opposite sidewalls of the fourth pattern, removing the third pattern and the fourth pattern, and etching the substrate using the first lower spacers and the second spacers as etch masks.Type: ApplicationFiled: March 28, 2016Publication date: October 20, 2016Inventors: Seung-Jin MUN, Dong-Hoon KHANG, Woo-Ram KIM, Cheol KIM, Dong-Seok LEE, Yong-Joon CHOI, Seung-Mo HA, Do-Hyoung KIM
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Publication number: 20160218010Abstract: A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.Type: ApplicationFiled: December 21, 2015Publication date: July 28, 2016Inventors: Bok-Young LEE, Yoo-Jung LEE, Dong-Hoon KHANG, Do-Hyoung KIM, Cheol KIM, In-Hee LEE, Ji-Eun HAN