Patents by Inventor Dong Hyeon Jang
Dong Hyeon Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140154839Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.Type: ApplicationFiled: December 2, 2013Publication date: June 5, 2014Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park
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Patent number: 8743582Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.Type: GrantFiled: May 25, 2011Date of Patent: June 3, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee
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Patent number: 8735276Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.Type: GrantFiled: February 3, 2012Date of Patent: May 27, 2014Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Hyun-Soo Chung, Jae-Shin Cho, Dong-Ho Lee, Dong-Hyeon Jang, Seong-Deok Hwang, Seung-Duk Baek
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Publication number: 20140057430Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.Type: ApplicationFiled: November 5, 2013Publication date: February 27, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Ho-Jin LEE, Tae-Je CHO, Dong-Hyeon JANG, Ho-Geon SONG, Se-Young JEONG, Un-Byoung KANG, Min-Seung YOON
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Patent number: 8637969Abstract: A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the firstType: GrantFiled: June 3, 2013Date of Patent: January 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Teak-hoon Lee, Won-keun Kim, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im
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Patent number: 8637350Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.Type: GrantFiled: April 4, 2012Date of Patent: January 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park
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Patent number: 8592991Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.Type: GrantFiled: September 17, 2011Date of Patent: November 26, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Jin Lee, Tae-Je Cho, Dong-Hyeon Jang, Ho-Geon Song, Se-Young Jeong, Un-Byoung Kang, Min-Seung Yoon
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Publication number: 20130264706Abstract: A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the firstType: ApplicationFiled: June 3, 2013Publication date: October 10, 2013Inventors: Teak-hoon Lee, Won-keun Kim, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im
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Patent number: 8455301Abstract: A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips.Type: GrantFiled: September 23, 2011Date of Patent: June 4, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Teak-hoon Lee, Won-keun Kim, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im
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Patent number: 8368231Abstract: A method for manufacturing chip stack packages may include: providing at least two wafers, each wafer having a plurality of chips, and scribe lanes formed between and separating adjacent chips; forming a plurality of via holes in peripheral portions of the scribe lanes; forming connection vias by filling the via holes; establishing electrical connections between the chip pads and corresponding connection vias; removing material from the back sides of the wafers to form thinned wafers; separating the thinned wafers into individual chips by removing a central portion of each scribe lane; attaching a first plurality of individual chips to a test wafer; attaching a second plurality of individual chips to the first plurality of individual chips to form a plurality of chip stack structures; encapsulating the plurality of chip stack structures; and separating the plurality of chip stack structures to form individual chip stack packages.Type: GrantFiled: June 6, 2011Date of Patent: February 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kang-Wook Lee, Gu-Sung Kim, Dong-Hyeon Jang, Seung-Duk Baek, Jae-Sik Chung
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Patent number: 8362621Abstract: A microelectronic structure includes a conductive pad on a substrate. The conductive pad includes first and second openings extending therethrough. A first conductive via on the conductive pad extends through the first opening in the conductive pad into the substrate. A second conductive via on the conductive pad adjacent the first conductive via extends through the second opening in the conductive pad into the substrate. At least one of the conductive vias may be electrically isolated from the conductive pad. Related devices and fabrication methods are also discussed.Type: GrantFiled: February 26, 2009Date of Patent: January 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ho Jin Lee, Dong Hyeon Jang, Nam Seog Kim, In Young Lee, Ha Young Yim
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Publication number: 20120292195Abstract: An apparatus for electroplating a semiconductor device includes a plating bath accommodating a plating solution, and a paddle in the plating bath, the paddle including a plurality of holes configured to pass the plating solution through the paddle toward a substrate, and a plating solution flow reinforcement portion configured to selectively reinforce a flow of the plating solution to a predetermined area of the substrate, the predetermined area of the substrate being an area requiring a relatively increased supply of metal ions of the plating solution.Type: ApplicationFiled: April 3, 2012Publication date: November 22, 2012Inventors: Ui Hyoung LEE, Ju-Il Choi, Jae-Hyun Phee, Dong Hyeon Jang, Jeong-Woo Park
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Publication number: 20120282735Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.Type: ApplicationFiled: April 4, 2012Publication date: November 8, 2012Inventors: Jung-seok Ahn, Dong-hyeon Jang, Ho-geon Song, Sung-jun Im, Chang-seong Jeon, Teak-hoon Lee, Sang-sick Park
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Publication number: 20120133048Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.Type: ApplicationFiled: September 17, 2011Publication date: May 31, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-Jin LEE, Tae-Je CHO, Dong-Hyeon JANG, Ho-Geon SONG, Se-Young JEONG, Un-Byoung KANG, Min-Seung YOON
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Publication number: 20120129334Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.Type: ApplicationFiled: February 3, 2012Publication date: May 24, 2012Applicant: Samsung Electronics Co., LtdInventors: Hyun-Soo CHUNG, Jae-Shin Cho, Dong-Ho Lee, Dong-Hyeon Jang, Seong-Deok Hwang, Seung-Duk Baek
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Publication number: 20120088332Abstract: A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips.Type: ApplicationFiled: September 23, 2011Publication date: April 12, 2012Inventors: Teak-hoon Lee, Won-Keun Kim, Dong-hyeon Jang, He-geon Song, Sung-jun Im
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Publication number: 20120077314Abstract: Methods of fabricating a semiconductor stack package having a high capacity, a small volume and reliability. According to the method of fabricating a semiconductor stack package, a first semiconductor substrate including a plurality of first semiconductor chips is attached to a chip protection film. The chip protection film is expanded such that the plurality of the first semiconductor chips are spaced apart from each other. A plurality of second semiconductor chips are attached to the plurality of the first semiconductor chips, respectively. A molding layer is formed between the plurality of the first semiconductor chips and between the plurality of the second semiconductor chips. The molding layer and the chip protection film are sawed to separate the semiconductor stack package comprising the first semiconductor chip and the second semiconductor chip into a unit.Type: ApplicationFiled: September 23, 2011Publication date: March 29, 2012Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-sick PARK, Dong-hyeon JANG, Chang-seong JEON, Teak-boon LEE
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Patent number: 8119448Abstract: A semiconductor chip comprises a substrate including a front surface and a rear surface, the substrate having a first via hole formed in the front surface and a second via hole formed in the rear surface, a first conductive plug formed on the substrate, the first conductive plug including a first portion formed in the first via hole and a second portion protruding from the front surface of the substrate, and a second conductive plug formed on the first conductive plug, the second conductive plug having a smaller cross-sectional area than the first conductive plug.Type: GrantFiled: June 17, 2010Date of Patent: February 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Son-Kwan Hwang, In-Young Lee, Ho-Jin Lee, Dong-Hyeon Jang
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Patent number: 8110922Abstract: A wafer level semiconductor module may include a module board and an IC chip set mounted on the module board. The IC chip set may include a plurality of IC chips having scribe lines areas between the adjacent IC chips. Each IC chip may have a semiconductor substrate having an active surface with a plurality of chip pads and a back surface. A passivation layer may be provided on the active surface of the semiconductor substrate of each IC chip and may having openings through which the chip pads may be exposed. Sealing portions may be formed in scribe line areas.Type: GrantFiled: October 8, 2009Date of Patent: February 7, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Soo Chung, Seung-Duk Baek, Dong-Ho Lee, Dong-Hyeon Jang, Seong-Deok Hwang
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Publication number: 20110292708Abstract: A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.Type: ApplicationFiled: May 25, 2011Publication date: December 1, 2011Inventors: Uk-song Kang, Dong-hyeon Jang, Seong-jin Jang, Hoon Lee, Jin-ho Kim, Nam-seog Kim, Byung-sik Moon, Woo-dong Lee