Abstract: The memory device includes a plurality of memory blocks that can individually operate in either a multi-bit per memory cell mode or a single-bit per memory cell mode. Certain voltage parameters during programming and reading are shared between these two operating modes, and certain voltage parameters are unique to each operating mode. One unique voltage parameter is a pass voltage VREADK that is applied to word lines adjacent a selected word line being read. Another unique voltage parameter is a VSGD voltage that is applied to a select gate drain transistor during programming. Yet another unique voltage parameter is an inhibit voltage that is applied to a bit line coupled with a memory cell being inhibited from programming while other memory cells are programmed.

Abstract: An all-printed physically unclonable function based on a single-walled carbon nanotube network. The network may be a mixture of semiconducting and metallic nanotubes randomly tangled with each other through the printing process. The unique distribution of carbon nanotubes in a network can be used for authentication, and this feature can be a secret key for a high level hardware security. The carbon nanotube network does not require any advanced purification process, alignment of nanotubes, high-resolution lithography and patterning. Rather, the intrinsic randomness of carbon nanotubes is leveraged to provide the unclonable aspect.

Abstract: A single input multiple output nanomaterial based gas sensor having multiple terminals situated on a single sensor device, providing a N(N?1)/2 measurements for a single device. Resistance is measured from any arbitrary pair of electrodes; repeating the measurements for all combinations of electrode pairs creates the data set. The gas sensor response is the ratio of resistance shift over the initial resistance (Rt?Ro)/Ro, where Rt and Ro are resistance upon gas exposure and initial resistance, respectively. The sensor response time is the time needed to reach a stable output signal when an external stimulus is introduced.

Abstract: Disclosed are a hardware-based selective security apparatus and a security method using the same. The security apparatus according to an embodiment of the present invention includes: a transistor including a source electrode, a drain electrode, and a gate electrode composed of at least two electrodes; and a controller which selectively sets a security level 1 or a security level 2 by controlling a magnitude of a voltage which is applied to the gate electrode. According to the present invention, since there is no necessity of an additional space for a separate chip required by an existing hardware based security method, it is possible to obtain a recoverable hardware based security method which uses spaces usefully and has economic efficiency. Also, a recoverable security level and an irrecoverable security level are selectively applied, so that it is possible to implement an enhanced hardware-based security method.