Abstract: A semiconductor system includes a semiconductor device and a controller. The semiconductor device includes a first memory rank and is configured to perform, in response to receiving a first write command, a first write operation of writing first data to the first memory rank. The semiconductor device includes a second memory rank and is configured to perform, in response to receiving a second write command, a second write operation of writing second data to the second memory rank. The controller is configured to receive at least one write request and responsively generate the first and second write commands separated in time so that a transition time interval between generation of the first write command and generation of the second write command is based on the second memory rank being different from the first memory rank and based on a comparison of a write preamble period to a write post-amble period.

Abstract: A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.

Abstract: A fusing device of which a lifespan may be increased by stably supplying a lubricant to a fusing belt, and an image forming apparatus including the same are provided.

Abstract: A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.

Abstract: A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.

Abstract: A semiconductor device includes a detection signal generation circuit generating a detection signal by detecting a phase difference of an input signal and an internal clock, and generating delayed input signals by delaying the input signal. The semiconductor device further includes an output enable signal generation circuit outputting an output enable signal by selecting one of the delayed input signals in response to the detection signal and latching the selected one of the delayed input signals in synchronization with the internal clock. The output enable signal may initiate a data transfer operation.

Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.

Abstract: A method includes performing a first write leveling training operation and performing a second write leveling training operation. The first write leveling training operation is performed to generate transmission data based on a data strobe signal and an internal command pulse and to generate a latency code. The second write leveling training operation is performed to generate the transmission data based on the data strobe signal and the internal command pulse.

Abstract: The present invention relates to a soft high-silicon steel sheet, and more particularly, to a soft high-silicon steel sheet which has ductility even if the silicon content thereof is greater than 4%, and can thus be manufactured into a steel sheet having a high silicon content only by means of rolling without an additional siliconizing process. The soft high-silicon steel sheet may include a silicon content greater than 4 wt % and less than or equal to 7 wt % and 1 to 20% of chromium, or may include 5 to 7 wt % of Si+Al and 1 to 20 wt % of chromium.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.

Abstract: A semiconductor device includes an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit is configured to generate an internal command pulse based on a write signal, a latency code, and an offset code. The sense data generation circuit is configured to generate a sense data based on the internal command pulse and an internal data strobe signal and configured to generate the sense data based on the internal command pulse and a delayed strobe signal.

Abstract: The present invention discloses an encoding apparatus using a Discrete Cosine Transform (DCT) scanning, which includes a mode selection means for selecting an optimal mode for intra prediction; an intra prediction means for performing intra prediction onto video inputted based on the mode selected in the mode selection means; a DCT and quantization means for performing DCT and quantization onto residual coefficients of a block outputted from the intra prediction means; and an entropy encoding means for performing entropy encoding onto DCT coefficients acquired from the DCT and quantization by using a scanning mode decided based on pixel similarity of the residual coefficients.