Patents by Inventor Dong Oog Kim
Dong Oog Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7883981Abstract: Embodiments relate to a flash memory device and a method for manufacturing a flash memory device. According to embodiments, a method may include forming a gate on and/or over a semiconductor substrate on and/or over which a device isolation film may be formed, forming a first spacer including a first oxide pattern and a first nitride pattern on and/or over side walls of the gate, forming a source and drain area on and/or over the semiconductor substrate using the gate and spacer as masks, removing the first nitride pattern of the first spacer, and forming a second spacer including a second oxide film pattern and a second nitride film pattern on and/or over the side walls of the gate by performing an annealing process on and/or over the semiconductor substrate on and/or over which the first oxide film pattern is formed.Type: GrantFiled: December 17, 2008Date of Patent: February 8, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Dong-Oog Kim
-
Patent number: 7666740Abstract: A nonvolatile semiconductor memory device that realizes a multi-bit cell and a method for manufacturing the same includes manufacturing the nonvolatile semiconductor memory device to be capable of storing multi-bit data, for example, 4-bit data, in a single memory cell and, as a result, the integration degree of a NOR type nonvolatile semiconductor memory device can be improved.Type: GrantFiled: September 13, 2007Date of Patent: February 23, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Dong-Oog Kim
-
Patent number: 7572696Abstract: The present invention provides a method of forming a gate in a flash memory device. The method includes: forming a oxide layer on a semiconductor substrate; forming a stacked structure including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate by patterning them on the semiconductor substrate; exposing portions of the semiconductor substrate below the field oxide layer by selectively etching the field oxide layer adjacent to the source region in order to form a common source; performing subsequent etching for removing oxides between the control gates; and forming an oxide layer covering the semiconductor substrate and both sidewalls of the floating gate and control gate.Type: GrantFiled: December 29, 2005Date of Patent: August 11, 2009Assignee: Dongbu HiTek Co., Ltd.Inventor: Dong-Oog Kim
-
Publication number: 20090159953Abstract: Embodiments relate to a flash memory device and a method for manufacturing a flash memory device. According to embodiments, a method may include forming a gate on and/or over a semiconductor substrate on and/or over which a device isolation film may be formed, forming a first spacer including a first oxide pattern and a first nitride pattern on and/or over side walls of the gate, forming a source and drain area on and/or over the semiconductor substrate using the gate and spacer as masks, removing the first nitride pattern of the first spacer, and forming a second spacer including a second oxide film pattern and a second nitride film pattern on and/or over the side walls of the gate by performing an annealing process on and/or over the semiconductor substrate on and/or over which the first oxide film pattern is formed.Type: ApplicationFiled: December 17, 2008Publication date: June 25, 2009Inventor: Dong-Oog Kim
-
Patent number: 7435647Abstract: A flash memory device that has a structure capable of preventing gate stack damage, and a method of manufacturing the same, is presented. The method includes forming a first photo resist pattern to open a common source region on a substrate where a shallow trench isolation region, a tunnel oxide layer, and a gate stack including a floating gate, a dielectric layer and a control gate are formed, removing an insulating layer in the shallow trench isolation region with using the first photo resist pattern as a mask, and removing the first photo resist pattern. The method further includes depositing a buffer oxide layer on surface of the substrate to cover the gate stack and the common source region, forming a second photo resist pattern on surface of the substrate including the buffer oxide layer to open the common source region, and injecting dopants to the common source region by using the second photo resist pattern as a mask.Type: GrantFiled: December 23, 2005Date of Patent: October 14, 2008Assignee: Olympus CorporationInventor: Dong Oog Kim
-
Patent number: 7396723Abstract: A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over a semiconductor substrate; forming a gate oxide layer over a top of the semiconductor substrate exposed through the mask pattern; forming access gates which are self-aligned with both side walls of the mask pattern, over a top of the gate oxide layer; removing the mask pattern; forming first dielectric spacers to be attached to side walls of the access gates; forming an insulating layer adapted to cover the access gates and the first dielectric spacers; and forming two cell gates, which are self-aligned with opposite side walls of the two access gates, respectively, each first dielectric spacer being interposed between a corresponding cell gate and a corresponding access gate, the cell gates separately arranged over a top of the insulating layer.Type: GrantFiled: December 20, 2006Date of Patent: July 8, 2008Assignee: Dongbu HiTek Co., Ltd.Inventor: Dong-Oog Kim
-
Publication number: 20080157179Abstract: A nonvolatile memory device can include source selection lines, word lines, and a drain selection line formed over a substrate; spacers formed on sidewalls of the source selection lines and the drain selection line; source/drain electrodes having a lightly doped drain structure formed in the substrate; a buffer layer formed over the substrate including over the spacers; and a passivation layer composed of nitrogen gas formed over the buffer layer.Type: ApplicationFiled: December 17, 2007Publication date: July 3, 2008Inventor: Dong-Oog Kim
-
Publication number: 20080157178Abstract: A flash memory device and fabricating method thereof are provided. A device isolating layer, a tunnel oxide film, and a floating gate can be formed on a substrate. An oxide-nitride-oxide (ONO) layer can be formed over the substrate, and a control gate can be formed on the ONO layer. A spacer can be formed of a high-temperature oxide film and a nitride film at sidewalls of the control gate.Type: ApplicationFiled: November 8, 2007Publication date: July 3, 2008Inventor: Dong Oog Kim
-
Publication number: 20080087936Abstract: A nonvolatile semiconductor memory device that realizes a multi-bit cell and a method for manufacturing the same includes manufacturing the nonvolatile semiconductor memory device to be capable of storing multi-bit data, for example, 4-bit data, in a single memory cell and, as a result, the integration degree of a NOR type nonvolatile semiconductor memory device can be improved.Type: ApplicationFiled: September 13, 2007Publication date: April 17, 2008Inventor: Dong-Oog Kim
-
Publication number: 20070148866Abstract: A method of manufacturing an EEPROM device can reduce the cell area. The method of manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) includes forming a mask pattern over a semiconductor substrate; forming a gate oxide layer over a top of the semiconductor substrate exposed through the mask pattern; forming access gates which are self-aligned with both side walls of the mask pattern, over a top of the gate oxide layer; removing the mask pattern; forming first dielectric spacers to be attached to side walls of the access gates; forming an insulating layer adapted to cover the access gates and the first dielectric spacers; and forming two cell gates, which are self-aligned with opposite side walls of the two access gates, respectively, each first dielectric spacer being interposed between a corresponding cell gate and a corresponding access gate, the cell gates separately arranged over a top of the insulating layer.Type: ApplicationFiled: December 20, 2006Publication date: June 28, 2007Inventor: Dong-Oog Kim
-
Patent number: 7211498Abstract: A method including forming a first mask material layer on a semiconductor substrate in order to mask a cell region and to not mask a peripheral circuit region. The method further includes forming a second mask material layer on an entire surface of the substrate in the cell region and peripheral circuit region, simultaneously forming a trench having a first depth in the cell region and a trench having a second depth in the peripheral circuit region, where the second depth is greater than the first depth. The method also includes filling an insulation layer into an entire surface of the substrate including trenches, planarizing the insulation material layer and the second mask material layer to a degree that the first mask material layer is exposed, and respectively forming an STI isolation layer in both the cell region and the peripheral circuit region by removing the first and second mask material layer.Type: GrantFiled: December 30, 2005Date of Patent: May 1, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Dong-Oog Kim
-
Patent number: 7195977Abstract: A method for fabricating the semiconductor device includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; forming gate lines on the field oxide regions and the gate oxide lines, the gate lines being substantially perpendicular to the field oxide regions; etching the gate oxide lines and the field oxide regions between the gate lines; and forming a self-aligned source (SAS) region by injecting impurity ions into the etched regions, the impurity ion being injected in a direction at a predetermined angle other than 90° relative to the semiconductor substrate.Type: GrantFiled: October 1, 2004Date of Patent: March 27, 2007Assignee: Dongbu Electronics Co., Ltd.Inventors: Sung Mun Jung, Dong Oog Kim
-
Publication number: 20070066030Abstract: A method including forming a first mask material layer on a semiconductor substrate in order to mask a cell region and to not mask a peripheral circuit region. The method further includes forming a second mask material layer on an entire surface of the substrate in the cell region and peripheral circuit region, simultaneously forming a trench having a first depth in the cell region and a trench having a second depth in the peripheral circuit region, where the second depth is greater than the first depth. The method also includes filling an insulation layer into an entire surface of the substrate including trenches, planarizing the insulation material layer and the second mask material layer to a degree that the first mask material layer is exposed, and respectively forming an STI isolation layer in both the cell region and the peripheral circuit region by removing the first and second mask material layer.Type: ApplicationFiled: December 30, 2005Publication date: March 22, 2007Applicant: DongbuAnam Semiconductor Inc.Inventor: Dong-Oog Kim
-
Publication number: 20060160308Abstract: The present invention provides a method of forming a gate in a flash memory device. The method includes: forming a oxide layer on a semiconductor substrate; forming a stacked structure including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate by patterning them on the semiconductor substrate; exposing portions of the semiconductor substrate below the field oxide layer by selectively etching the field oxide layer adjacent to the source region in order to form a common source; performing subsequent etching for removing oxides between the control gates; and forming an oxide layer covering the semiconductor substrate and both sidewalls of the floating gate and control gate.Type: ApplicationFiled: December 29, 2005Publication date: July 20, 2006Inventor: Dong-Oog Kim
-
Publication number: 20060148201Abstract: The present invention provides a method of forming an STI region in a flash memory device. The method includes: forming a pad oxide layer on a semiconductor substrate; forming a hard mask on the pad oxide layer; forming a recess groove below the hard mask by etching a portion of the pad oxide layer exposed by the hard mask and a portion of the pad oxide layer below the hard mask; forming a trench having a round edge by etching a portion of the semiconductor substrate exposed by the hard mask and a portion of the semiconductor substrate exposed in the recess groove; and forming an insulation layer filling in the trench.Type: ApplicationFiled: December 30, 2005Publication date: July 6, 2006Inventor: Dong-Oog Kim
-
Publication number: 20060148176Abstract: A method of manufacturing a gate in a flash memory device. The method includes forming a stacking structure including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate on a semiconductor substrate. The further includes removing a remaining portion of the tunnel oxide layer exposed by the control gate by wet etching to a degree that the semiconductor substrate is exposed, and forming an oxide layer covering the exposed portion of the semiconductor substrate and both sidewalls of the floating gate and the control gate.Type: ApplicationFiled: December 30, 2005Publication date: July 6, 2006Applicant: DongbuAnam Semiconductor Inc.Inventors: Dong-Oog Kim, Chang-Hun Han
-
Publication number: 20060148175Abstract: A method of manufacturing a semiconductor device includes forming a polysilicon layer on a trench isolation layer and a tunnel oxide layer formed on a semiconductor substrate, and doping the polysilicon layer with germanium or argon. The doped polysilicon layer is patterned to form a floating gate electrode layer pattern. A charge-trapping layer is formed on the floating gate electrode layer pattern, and a control gate electrode layer pattern is formed on the charge-trapping layer.Type: ApplicationFiled: December 30, 2005Publication date: July 6, 2006Applicant: DongbuAnam Semiconductor Inc.Inventors: Dong-Oog Kim, Chang-Hun Han
-
Publication number: 20060148198Abstract: An exemplary method of forming a device isolation region in a semiconductor device according to an embodiment of the present invention includes forming a sacrificial layer and a hard mask on a substrate; selectively etching the hard mask, the sacrificial layer, and the substrate so as to form a trench; forming a thermal oxide layer on the trench; forming an insulation layer on the thermal oxide layer to fill the trench; polishing the insulation layer and the hard mask so as to leave the hard mask with a predetermined thickness; removing the remaining hard mask and the sacrificial layer; and removing a height difference between the device isolation region and the substrate by partially removing the upper portion of the device isolation region by wet etching.Type: ApplicationFiled: December 29, 2005Publication date: July 6, 2006Inventor: Dong-Oog Kim
-
Patent number: 6984590Abstract: A method of manufacturing an EEPROM device is disclosed. An example method forms a screen oxide film on a semiconductor substrate, forms a first ion implantation mask defining a gate insulating film forming region on the screen oxide film, and performs a first ion implantation on the semiconductor substrate and the first ion implantation mask. The example method also performs a first annealing of the semiconductor substrate, removes the screen oxide film and the first ion implantation mask, and forms a gate oxide film on the semiconductor substrate. In addition, the example method forms a second ion implantation mask defining a gate insulating film forming region on the gate oxide film, performs a second ion implantation on the semiconductor substrate and the second ion implantation mask, performs a second annealing for the semiconductor substrate, removes the second ion implantation mask; and forms a tunnel oxide film on the gate oxide film.Type: GrantFiled: December 22, 2003Date of Patent: January 10, 2006Assignee: Dongbu Anam Semiconductor Inc.Inventors: Chang Hun Han, Dong Oog Kim
-
Publication number: 20040137674Abstract: A method of manufacturing an EEPROM device is disclosed. An example method forms a screen oxide film on a semiconductor substrate, forms a first ion implantation mask defining a gate insulating film forming region on the screen oxide film, and performs a first ion implantation on the semiconductor substrate and the first ion implantation mask. The example method also performs a first annealing of the semiconductor substrate, removes the screen oxide film and the first ion implantation mask, and forms a gate oxide film on the semiconductor substrate. In addition, the example method forms a second ion implantation mask defining a gate insulating film forming region on the gate oxide film, performs a second ion implantation on the semiconductor substrate and the second ion implantation mask, performs a second annealing for the semiconductor substrate, removes the second ion implantation mask; and forms a tunnel oxide film on the gate oxide film.Type: ApplicationFiled: December 22, 2003Publication date: July 15, 2004Inventors: Chang Hun Han, Dong Oog Kim