Patents by Inventor Dong Seok Chun
Dong Seok Chun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11417562Abstract: One embodiment of a substrate supporting apparatus comprises: a support member for supporting a substrate; and a temperature compensating member disposed at the edge of the support member, and compensating the temperature of the substrate, wherein the support member may be made of a light-transmissive material, the temperature compensating member may be made of an opaque material, and the surface of the temperature compensating member may be made of a material having corrosion resistance against a cleaning gas.Type: GrantFiled: June 25, 2018Date of Patent: August 16, 2022Inventors: Dong Seok Chun, Jeong Mi Kim, Jong Sik Kim, Won Woo Jung, Min Ho Cheon, Chul Joo Hwang
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Publication number: 20210082738Abstract: One embodiment of a substrate supporting apparatus comprises: a support member for supporting a substrate; and a temperature compensating member disposed at the edge of the support member, and compensating the temperature of the substrate, wherein the support member may be made of a light-transmissive material, the temperature compensating member may be made of an opaque material, and the surface of the temperature compensating member may be made of a material having corrosion resistance against a cleaning gas.Type: ApplicationFiled: June 25, 2018Publication date: March 18, 2021Inventors: Dong Seok CHUN, Jeong Mi KIM, Jong Sik KIM, Won Woo JUNG, Min Ho CHEON, Chul Joo HWANG
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Publication number: 20180130674Abstract: Disclosed are an apparatus and method for processing a substrate. The apparatus includes a chamber, a susceptor disposed in a lower portion of the chamber, a chamber lid disposed on the susceptor, a first source gas distributor installed in the chamber lid to distribute a source gas, a second source gas distributor installed in the chamber lid to distribute a source gas, and a first purge gas distributor installed in the chamber lid to distribute a purge gas. At least one substrate is disposed on the susceptor, and the first purge gas distributor is installed between the first and second source gas distributors.Type: ApplicationFiled: April 18, 2016Publication date: May 10, 2018Inventors: Tae Seong HAN, Dae Bong KANG, Jae Chan KWAK, Ka Lam KIM, Doo Young KIM, Dong Won SEO, Sang Du LEE, Seong Kwang LEE, Byoung Ha CHO, Dong Seok CHUN, Chul-Joo HWANG
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Patent number: 6407448Abstract: A stackable Ball Grid Array (BGA) semiconductor chip package and a fabrication method thereof increases reliability and mount density of a semiconductor package. The stackable BGA semiconductor chip package includes a supporting member that includes a supporting plate and a supporting frame formed on edges of the supporting plate. Conductive patterns are formed in and extend through the supporting member. First metal traces are formed on a bottom of the supporting plate and the first metal traces are connected to first ends of the conductive patterns in the supporting member. Second metal traces are attached to an upper surface of a semiconductor chip, and the semiconductor chip is attached to the supporting member. The second metal traces are connected to bond pads of the chip, and to upper ends of the conductive patterns in the supporting member. A plurality of conductive balls are then attached to exposed portions of the first and/or the second metal traces.Type: GrantFiled: August 6, 2001Date of Patent: June 18, 2002Assignee: Hyundai Electronics Industries Co., Inc.Inventor: Dong Seok Chun
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Publication number: 20010048151Abstract: A stackable Ball Grid Array (BGA) semiconductor chip package and a fabrication method thereof increases reliability and mount density of a semiconductor package. The stackable BGA semiconductor chip package includes a supporting member that includes a supporting plate and a supporting frame formed on edges of the supporting plate. Conductive patterns are formed in and extend through the supporting member. First metal traces are formed on a bottom of the supporting plate and the first metal traces are connected to first ends of the conductive patterns in the supporting member. Second metal traces are attached to an upper surface of a semiconductor chip, and the semiconductor chip is attached to the supporting member. The second metal traces are connected to bond pads of the chip, and to upper ends of the conductive patterns in the supporting member. A plurality of conductive balls are then attached to exposed portions of the first and/or the second metal traces.Type: ApplicationFiled: August 6, 2001Publication date: December 6, 2001Applicant: Hyundai Electronics Industries Co., Inc.Inventor: Dong Seok Chun
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Patent number: 6291259Abstract: A stackable Ball Grid Array (BGA) semiconductor chip package and a fabrication method thereof increases reliability and mount density of a semiconductor package. The stackable BGA semiconductor chip package includes a supporting member that includes a supporting plate and a supporting frame formed on edges of the supporting plate. Conductive patterns are formed in and extend through the supporting member. First metal traces are formed on a bottom of the supporting plate and the first metal traces are connected to first ends of the conductive patterns in the supporting member. Second metal traces are attached to an upper surface of a semiconductor chip, and the semiconductor chip is attached to the supporting member. The second metal traces are connected to bond pads of the chip, and to upper ends of the conductive patterns in the supporting member. A plurality of conductive balls are then attached to exposed portions of the first and/or the second metal traces.Type: GrantFiled: January 28, 1999Date of Patent: September 18, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Dong Seok Chun
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Patent number: 6066887Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads on its top surface, a plurality of inner leads located above the semiconductor chip and electrically connected to the bonding pads by wire, a plurality of outer leads extending from the respective inner leads, and at least one bus bar formed lower than the inner leads, to prevent electrical shorts and improve reliability of the package.Type: GrantFiled: February 13, 1998Date of Patent: May 23, 2000Assignee: LG Semicon Co., Ltd.Inventors: Joon Ki Hong, Dong Seok Chun
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Patent number: 5933709Abstract: A semiconductor package including a first heat slug having a substantially flat shape and a second heat slug coupled to the first heat slug. A semiconductor chip is mounted on an inner surface of the first heat slug and a third heat slug is fixed to a central portion of the semiconductor chip. A plurality of inner leads are fixed to sides of the semiconductor chip and outer leads extend from the inner leads and are bent outward with respect to the inner leads. Conductive wires connect the inner leads to the semiconductor chip. A mold portion seals the semiconductor or chip, the inner leads, a portion of the outer leads, and the conductive wire.Type: GrantFiled: July 16, 1997Date of Patent: August 3, 1999Assignee: LG Semicon Co., LtdInventor: Dong-Seok Chun
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Patent number: 5821605Abstract: A semiconductor package is disclosed including a semiconductor chip having a plurality of bonding pads on its top surface; a plurality of inner leads located above the semiconductor chip and electrically connected to the bonding pads by wire; a plurality of outer leads extending from the respective inner leads; and at least one bus bar for power supply and ground formed to be lower than the inner leads above the semiconductor chip. A method of packaging a semiconductor device is disclosed including the steps of: providing a semiconductor chip having a plurality of bonding pads on its top surface; arranging a plurality of inner leads and a plurality of outer leads extending therefrom above the semiconductor chip; and arranging bus bars for power supply and ground to be lower than the inner leads above the semiconductor chip.Type: GrantFiled: August 2, 1995Date of Patent: October 13, 1998Assignee: LG Semicon Co, Ltd.Inventors: Joon Ki Hong, Dong Seok Chun