Patents by Inventor Dong Sheng Rao

Dong Sheng Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230359357
    Abstract: A write control method based on write behavior prediction, a memory storage device, and a memory control circuit unit are provided. The method includes: monitoring a first data write behavior of a host system during a first time range; according to the first data write behavior, predicting a second data write behavior of the host system during a second time range; obtaining a first measurement parameter and a first target parameter corresponding to the first data write behavior; according to the first measurement parameter, the first target parameter, and the second data write behavior, determining a write control parameter; and sending a write command sequence according to the write control parameter to instruct a rewritable non-volatile memory module to perform a data write based on multiple write modes during the second time range.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 9, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Chih-Ling Wang, FAN YI, Kuai Cao, Yang Chen, Qin Qin Tao, Dong Sheng Rao
  • Patent number: 11803208
    Abstract: A timer calibration method and an electronic device are disclosed. The method includes: performing a fitting operation according to a clock frequency of a clock device and an output of a timer to generate a fitting function; obtaining a first value output by the timer; and adjusting the first value to be a second value according to the fitting function to calibrate the timer.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: October 31, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Yang Chen, Yue Hu, Dong Sheng Rao, Kuai Cao, Qin Qin Tao
  • Patent number: 11715532
    Abstract: A risk assessment method based on data priority, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a query command from a host system; in response to the query command, performing a data health detection on a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module stores data with multiple data priorities; generating risk assessment information according to a detection result, wherein the risk assessment information reflects a health degree of data with different data priorities in the rewritable non-volatile memory modules by different risk levels; and transmitting the risk assessment information to the host system.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: August 1, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Chih-Ling Wang, Yue Hu, Qin Qin Tao, Dong Sheng Rao, Shao Feng Yang, Yang Chen
  • Patent number: 11693567
    Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: July 4, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang, Xu Hui Cheng, Dong Sheng Rao
  • Publication number: 20230185329
    Abstract: A timer calibration method and an electronic device are disclosed. The method includes: performing a fitting operation according to a clock frequency of a clock device and an output of a timer to generate a fitting function; obtaining a first value output by the timer; and adjusting the first value to be a second value according to the fitting function to calibrate the timer.
    Type: Application
    Filed: January 11, 2022
    Publication date: June 15, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Yang Chen, Yue Hu, Dong Sheng Rao, Kuai Cao, Qin Qin Tao
  • Publication number: 20230127512
    Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.
    Type: Application
    Filed: November 22, 2021
    Publication date: April 27, 2023
    Applicant: Hefei Core Storage Electronic Limited
    Inventors: Qi-Ao Zhu, Jing Zhang, Kuai Cao, Xin Wang, Xu Hui Cheng, Dong Sheng Rao