Abstract: A wafer level chip scale package capable of reducing parasitic capacitances between a rerouting and the metal wiring of a wafer, and a method for manufacturing the same are provided. An embodiment of the wafer level chip scale package includes a wafer arranged with a plurality of bonding pads and an insulating member formed on the wafer so that the bonding pads are exposed. A rerouting is further formed on the insulating member in contact with the exposed bonding pads and an external connecting terminal is electrically connected to a portion of the rerouting. Here, the insulating member overlapping the rerouting is provided with a plurality of spaces in which air is trapped.

Abstract: A method for manufacturing of a lead-on-chip type semiconductor chip package is disclosed, which comprises the steps of coating a liquid polyimide coating material on the bonding faces of at least one of the inner leads and the bus bars of the lead frame and the semiconductor chip, attaching the semiconductor chip by using the cured liquid polyimide coating material as an attaching medium, and forming a package body for wrapping and protecting the semiconductor chip and bonding wires. Since the liquid polyimide coating material protects the wafer from which the chips are obtained and also serves as a bonding agent for the semiconductor chip at the same time, the semiconductor chip package according to the present invention can be protected from damage, such as by air bubbles, which are generated at the interface of the conventional polyimide tape, and by separation and expansion of adhesives.