Abstract: A chip-type electric double layer capacitor includes: a resin case having a housing space provided therein and formed of insulating resin; first and second external terminals inserted into the resin case by insert injection molding, each having a first portion exposed to an outer surface of the resin case for external contact and a second portion exposed to an inner surface of the housing space for internal contact; a sealing portion including a groove portion provided in the resin case along a circumference of at least one of the first and second external terminals and a resin filling the groove portion; and an electric double layer capacitor cell mounted in the housing space and electrically connected to the second portion of the first and second external terminals.

Abstract: A method of manufacturing a chip-type electric double layer capacitor, including: forming a lower case having an opened housing space and first and second external terminals buried therein, the first and second external terminals having first surfaces exposed to the housing space, respectively, and second surfaces exposed to an outer region of the lower case, respectively; mounting an electric double layer capacitor cell in the housing space such that the electric double layer capacitor cell is electrically connected to the first surfaces of the first and second external terminals exposed to the housing space; and mounting an upper cap on the lower case so as to cover the housing space.

Abstract: A chip-type electric double layer capacitor includes: a resin case having a housing space provided therein and formed of insulating resin; first and second external terminals inserted into the resin case by insert injection molding, each having a first portion exposed to an outer surface of the resin case for external contact and a second portion exposed to an inner surface of the housing space for internal contact; a sealing portion including a groove portion provided in the resin case along a circumference of at least one of the first and second external terminals and a resin filling the groove portion; and an electric double layer capacitor cell mounted in the housing space and electrically connected to the second portion of the first and second external terminals.

Abstract: An electric double layer capacitor (EDLC) includes an electric double layer cell and first and second external electrodes. The electric double layer cell includes a separator and at least one first polarizable electrode and at least one second polarizable electrode. The first and second external electrodes are formed at first and second side surfaces of the electric double layer cell facing each other, respectively. The first polarizable electrode includes a first current collection layer and a first active material layer formed on either surface of the first current collection layer facing the separator and the second polarizable electrode includes a second current collection layer and a second active material layer formed on either surface of the second current collection layer facing the separator.

Abstract: A method of manufacturing a chip-type electric double layer capacitor, including: forming a lower case having an opened housing space and first and second external terminals buried therein, the first and second external terminals having first surfaces exposed to the housing space, respectively, and second surfaces exposed to an outer region of the lower case, respectively; mounting an electric double layer capacitor cell in the housing space such that the electric double layer capacitor cell is electrically connected to the first surfaces of the first and second external terminals exposed to the housing space; and mounting an upper cap on the lower case so as to cover the housing space.

Abstract: The present invention provides a chip type electric double layer capacitor including: a lower case having an internal space of which an upper surface is opened and an external terminal of which portions exposed to a bottom of the internal space and the outside are connected to each other; an electric double layer capacitor cell disposed in the internal space of the lower case to be electrically connected to the portion of the external terminal, which is exposed to the bottom of the internal space; and an upper cap mounted on the lower case to cover the internal space, and a method for manufacturing the same.

Abstract: A method of manufacturing the electric double layer capacitor cell includes preparing first and second electrode sheets by printing electrode material onto conductive sheets, respectively, with the exception of regions to be provided as first and second terminal lead-out portions in the conductive sheets; punching the first and second electrode sheets so as to form a plurality of first and second unit electrodes, respectively, each first unit electrode having the first terminal lead-out portion and each second unit electrode having the second terminal lead-out portion; stacking the first and second electrode sheets with a separator interposed therebetween in order that the plurality of first and second unit electrodes are overlapped; and cutting the first and second electrode sheets being stacked into the first and second unit electrodes.

Abstract: There are provided methods of manufacturing an electric double layer capacitor cell and an electric double layer capacitor and an apparatus for manufacturing an electric double layer capacitor cell.

Abstract: There are provided methods of manufacturing an electric double layer capacitor cell and an electric double layer capacitor and an apparatus for manufacturing an electric double layer capacitor cell.

Abstract: There is provided an electric double layer capacitor and a method of manufacturing the same. The electric double layer capacitor includes first and second electrodes facing each other; and an ion-permeable separator interleaved between the first and second electrodes, wherein at least one of the first and second electrodes includes a metallic fiber being compressed to have pores therein and an electrode material filling the pores. The electric double layer capacitor has low equivalent series resistance (ESR) and high output density. Also, since the electrodes are formed to be thin, the electric double layer capacitor can be miniaturized.

Abstract: There are provided an electric double layer capacitor cell, an electric double layer capacitor package having the same, and methods of manufacturing the same. An electric double layer capacitor cell according to an aspect of the invention may include: a plurality of electric double layer capacitor unit cells stacked upon each other, wherein each of the plurality of electric double layer capacitor unit cells includes first and second current collectors having first and second lead terminal portions, respectively, first and second electrodes provided on the first and second current collectors, respectively, and a separator provided between the first and second electrodes, and the first and second electrode lead terminal portions each are combined into one to provide first and second bonding portions being connected to external terminals provided to apply electricity to the electric double layer capacitor unit cells.

Abstract: There is provided a chip-type electric double layer capacitor including: an exterior case having a housing space provided therein and formed of insulation resin; first and second external terminals buried in the exterior case, each having a plurality of first surfaces exposed to the housing space and a second surface exposed to an outside of the exterior case; and an electric double layer cell electrically connected to the plurality of first surfaces of the first and second external terminals exposed to the housing space. The chip-type electric double layer capacitor may be reduced in size and weight and increased in capacity. Also, the chip-type electric double layer capacitor allows for surface mounting without any additional structure and has low equivalent series resistance (ESR).

Abstract: There is provided a chip-type electric double layer capacitor comprising: a resin case having a housing space provided therein and formed of insulating resin and first and second external terminals inserted into the resin case by insert injection molding. Each of the external terminals has a first portion exposed to an outer surface of the resin case for external contact and a second portion exposed to an inner surface of the housing space for internal contact. a sealing portion includes a groove portion provided in the resin case along a circumference of at least one of the first and second external terminals and a resin filling the groove portion. An electric double layer capacitor cell is mounted in the housing space and electrically connected to the second portion of the first and second external terminals.

Abstract: The present invention provides a chip type electric double layer capacitor including: a lower case having an internal space of which an upper surface is opened and an external terminal of which portions exposed to a bottom of the internal space and the outside are connected to each other; an electric double layer capacitor cell disposed in the internal space of the lower case to be electrically connected to the portion of the external terminal, which is exposed to the bottom of the internal space; and an upper cap mounted on the lower case to cover the internal space, and a method for manufacturing the same.

Abstract: An electric double layer capacitor (EDLC) includes an electric double layer cell and first and second external electrodes. The electric double layer cell includes a separator and at least one first polarizable electrode and at least one second polarizable electrode. The first and second external electrodes are formed at first and second side surfaces of the electric double layer cell facing each other, respectively. The first polarizable electrode includes a first current collection layer and a first active material layer formed on either surface of the first current collection layer facing the separator and the second polarizable electrode includes a second current collection layer and a second active material layer formed on either surface of the second current collection layer facing the separator.

Abstract: The present invention relates to a chip-type electric double layer capacitor and a method for manufacturing a method for manufacturing the same. The chip-type electric double layer capacitor includes an electric double layer element including two electrodes that include two different polarities and electrode terminals protruded on sides opposite to each other, a first separator that prevents the two electrodes from being short-circuited, and a second separator that is disposed at a position opposed to the first separator on the basis of one electrode of the two electrodes; and a package including package terminals attached to the protruded electrode terminals of the two electrodes, which are formed on the bottom thereof and housing the electric double layer element, wherein the electric double layer element is wound on the basis of the protruded electrode terminals opposite to the two electrodes as a reference axis and the electrode terminals are attached to the package terminals, respectively.

Abstract: Disclosed is a package structure of a chip-type electric double layer capacitor which includes a lower package, which houses an electric double layer element and has a package terminal formed thereon to be electrically connected to the electric double layer element, and an upper package which is disposed on a top part of the lower package and seals the electric double layer element from the outside, wherein the package terminals are formed to be protruded from an internal bottom surface and an external bottom surface of the lower package, and the external bottom surface of the lower package has at least two pairs of protrusions formed thereon.

Abstract: A chip-type electric double layer capacitor includes: an exterior case including a housing space formed therein and formed of insulation resin; a first external terminal buried in the exterior case and including a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case; a second external terminal buried in the exterior case and including a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case; and an electric double layer cell disposed in the housing space so as to be electrically connected to the first surfaces of the first and second external terminals.