Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.

Abstract: An electrical device, such as a semiconductor device, and methods of manufacturing the same. A semiconductor device having a shallow trench isolation (STI) layer may include a pad oxide layer formed over a semiconductor substrate, a trench formed over the substrate, a liner insulating layer formed over the trench, a gap-fill insulating layer formed over the liner insulating layer and a gate layer formed over the substrate. The gap-fill insulating layer may have a relatively and/or substantially planar polished surface. Methods of fabricating a semiconductor device having a shallow trench isolation (STI) layer may include performing a first chemical mechanical polishing over a gap-fill insulating layer to expose and/or target a portion of a liner insulating layer and performing a second chemical mechanical polishing over a gap-fill insulating layer to remove a portion of a liner insulating layer.

Abstract: An electrical device, such as a semiconductor device, and methods of manufacturing the same. A semiconductor device having a shallow trench isolation (STI) layer may include a pad oxide layer formed over a semiconductor substrate, a trench formed over the substrate, a liner insulating layer formed over the trench, a gap-fill insulating layer formed over the liner insulating layer and a gate layer formed over the substrate. The gap-fill insulating layer may have a relatively and/or substantially planar polished surface. Methods of fabricating a semiconductor device having a shallow trench isolation (STI) layer may include performing a first chemical mechanical polishing over a gap-fill insulating layer to expose and/or target a portion of a liner insulating layer and performing a second chemical mechanical polishing over a gap-fill insulating layer to remove a portion of a liner insulating layer.

Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.

Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.

Abstract: An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate insulation layer on a semiconductor substrate; forming a plurality of gate electrodes on the gate insulation layer; forming pocket regions by a pocket ion implantation process using the gate electrode as an implantation mask; forming a capping electrode layer on the gate electrode by depositing a polysilicon layer; forming lightly doped regions by low-concentration ion implantation using the capping electrode layer as an implantation mask; forming spacer layers on the sidewall of the capping electrode layer; and forming source and drain regions by high concentration ion implantation using the spacer layers as an implantation mask. The method can suppress the occurrence of the punch-through phenomenon.

Abstract: A metal interconnection layout for a semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device can maintain a minimum design rule and secure a distance between via holes to inhibit a metal bridge phenomenon from being generated. The semiconductor device comprises a substrate, an interlayer dielectric, a first metal interconnection, and a second metal interconnection parallel to the first metal interconnection. The interlayer dielectric can be disposed on the substrate. The first metal interconnection is connected to the substrate or lower interconnect through at least one first via hole in the interlayer dielectric. The second metal interconnection is adjacent to the first metal interconnection and can be connected to the substrate or another lower interconnect through at least one second via hole in the interlayer dielectric.

Abstract: Disclosed is a method for fabricating a semiconductor device. The method can include forming a first barrier pattern to cover a first region of a semiconductor substrate while exposing second and third regions of the semiconductor substrate, forming a first oxide layer pattern on the second and third regions, forming a second barrier pattern to cover the third region while exposing the first and second regions, forming a second oxide layer pattern on the first and second regions, forming a third oxide layer pattern on the second region by removing the second and first oxide layer patterns formed on the first and third regions, forming a silicide metal layer on the first, second, and third regions, and selectively forming silicide on the first and third regions by performing an annealing process with respect to the silicide metal layer.

Abstract: A method of fabricating a metal interconnection of a semiconductor device is provided. According to an embodiment, spacers are formed at sidewalls of a first via hole in a first interlayer dielectric layer. Then, a second interlayer dielectric layer is deposited on the via hole having the spacers. A second via hole and trench are formed through the second interlayer dielectric layer and remaining first interlayer dielectric layer below the first via hole to expose a lower layer. Metal can be filled in the trench and second via hole to form a metal interconnection. Accordingly, the spacer can improve the cohesive property of the second interlayer dielectric layer, so voids can be inhibited from forming in the second interlayer dielectric layer.

Abstract: Disclosed is a method for fabricating a semiconductor device. The method can include forming a first barrier pattern to cover a first region of a semiconductor substrate while exposing second and third regions of the semiconductor substrate, forming a first oxide layer pattern on the second and third regions, forming a second barrier pattern to cover the third region while exposing the first and second regions, forming a second oxide layer pattern on the first and second regions, forming a third oxide layer pattern on the second region by removing the second and first oxide layer patterns formed on the first and third regions, forming a silicide metal layer on the first, second, and third regions, and selectively forming silicide on the first and third regions by performing an annealing process with respect to the silicide metal layer.

Abstract: A capacitor structure and a method of fabricating the capacitor structure wherein. The lower electrode and the upper electrode are constructed to be separated from each other by a predetermined interval and to be engaged with each other using a series of alternating ridges so that an effective surface area can increase within a limited area.

Abstract: Methods for fabricating a copper interconnect are disclosed. A disclosed method comprises: employing a damascene process to form a first trench in a first insulating layer; depositing a first barrier layer and a first copper layer on the first insulating layer; forming a bottom copper interconnect by planarizing the first copper layer; depositing and planarizing a second barrier layer; depositing a second insulating layer; forming a via hole in the second insulating layer; employing a damascene process to form a second trench in the second insulating layer; and forming a via and an upper copper interconnect by depositing a third barrier layer and a second copper layer on the second insulating layer.

Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.

Abstract: Disclosed is a method for forming a dual damascene pattern. The method includes the steps of forming a lower conductive structure on a lower insulating layer, forming a first protective film, a first insulating film, a second insulating film, a third insulating film, and a second protective film, sequentially, on the lower insulating layer and the lower conductive structure, forming a via hole up to a predetermined depth of the second insulating film through the second protective film and the third insulating film, forming a trench up to the predetermined depth of the second insulating film through the second protective film and the third insulating film, and simultaneously, extending the via hole up to a point at which the first protective film is exposed, and selectively etching the first protective film exposed through the via hole to expose the lower conductive pattern and form the dual damascene pattern.

Abstract: Methods of fabricating semiconductor devices are disclosed. One example method includes forming a gate oxide and a gate electrode on a semiconductor substrate; performing a first ion implantation process for the formation of an LDD (lightly doped drain) region in the substrate; forming spacers on the sidewalls of the gate electrode; performing a second ion implantation process for the formation of a junction region in the substrate using the spacers as mask; forming a trench for device isolation by removing selectively the top portion of the substrate between the spacers; forming a sidewall oxide layer on the resulting substrate; forming a diffusion barrier on the sidewall oxide layer; depositing a gap filling insulation layer over the diffusion barrier; planarizing the gap filling insulating layer; and removing selectively some part of the gap filling insulation layer to form contact holes.

Abstract: A method of fabricating an interconnection structure of a semiconductor device includes the steps of successively depositing an etch-stop layer and an intermetal insulating layer on a semiconductor substrate, forming a sacrificial insulating layer on the intermetal insulating layer, forming a photoresist pattern on the sacrificial insulating layer to define a trench formation region, etching the intermetal insulating layer using a mask of the photoresist pattern to form a trench, and etching the entire etch-stop layer.

Abstract: An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate insulation layer on a semiconductor substrate; forming a plurality of gate electrodes on the gate insulation layer; forming pocket regions by a pocket ion implantation process using the gate electrode as an implantation mask; forming a capping electrode layer on the gate electrode by depositing a polysilicon layer; forming lightly doped regions by low-concentration ion implantation using the capping electrode layer as an implantation mask; forming spacer layers on the sidewall of the capping electrode layer; and forming source and drain regions by high concentration ion implantation using the spacer layers as an implantation mask. The method can suppress the occurrence of the punch-through phenomenon.

Abstract: A method of manufacturing a semiconductor device consistent with embodiments of the present invention includes forming a first insulation layer on a semiconductor substrate provided with an isolation layer and an active region; exposing a part of the active region by patterning the first insulation layer; forming a second insulation layer on the patterned first insulation layer; forming a contact hole exposing the active region and the edge portion of the first insulation layer by patterning the second insulation layer; and forming a metal layer on the second insulation layer and the exposed active region. Consequently, a junction leakage current that may be generated at the interface between the active region and the isolation layer in forming the metal contact hole can be suppressed, so the yield and reliability of devices may be enhanced.

Abstract: The present invention relates to a method of forming damascene pattern in a semiconductor device, and the method includes forming an insulating layer on a bottom wiring, forming via holes exposing a part of the bottom wiring by removing the insulating layer selectively, filling insides of the via holes to a prescribed thickness, forming an anti-reflection layer on the via holes and the insulating layer, forming a mask pattern for trench etching on the insulating layer on which the anti-reflection layer is formed, and forming a damascene pattern using the mask pattern for trench etching. CD uniformity is improved by minimizing change of the critical dimension of the damascene pattern, thereby increasing reliability of the semiconductor device.

Abstract: Disclosed is a method for forming a dual damascene pattern. The method comprises the steps of forming a lower conductive structure on a lower insulating layer, forming a first protective film, a first insulating film, a second insulating film, a third insulating film, and a second protective film, sequentially, on the lower insulating layer and the lower conductive structure, forming a via hole up to a predetermined depth of the second insulating film through the second protective film and the third insulating film, forming a trench up to the predetermined depth of the second insulating film through the second protective film and the third insulating film, and simultaneously, extending the via hole up to a point at which the first protective film is exposed, and selectively etching the first protective film exposed through the via hole to expose the lower conductive pattern and form the dual damascene pattern.