Abstract: Systems, apparatuses and methods may provide technology for managing a runtime computing environment having tiered object memory placement that assigns a hotness score to an object having an object type based on an invocation count of objects referenced by a hot method, allocates a newly-created object to one of a hot object heap, said hot object heap assigned to store hot objects in a first memory tier, or a cold object heap, said cold object heap assigned to store cold objects in a second memory tier, based on the hotness score associated with the object type for the newly-created object, and migrates a plurality of objects between the hot object heap and the cold object heap based on a hotness score associated with each object. The technology may also operate the object migration in an execution thread independent of an execution thread for the object allocation.

Abstract: Data locality optimization through object relocation may be implemented in a virtual machine including a just-in-time compiler. The just-in-time compiler generates load instruction maps for each compiled method. A profile collector is coupled to the just-in-time compiler to receive hardware profiling support. The profile collector takes samples of data cache misses. A garbage collector is coupled to the profile collector. The garbage collector deduces types of objects from the cache miss samples and adjusts garbage collection object copying heuristics to relocate objects for better cache locality based on those types.

Abstract: Data locality optimization through object relocation may be implemented in a virtual machine including a just-in-time compiler. The just-in-time compiler generates load instruction maps for each compiled method. A profile collector is coupled to the just-in-time compiler to receive hardware profiling support. The profile collector takes samples of data cache misses. A garbage collector is coupled to the profile collector. The garbage collector deduces types of objects from the cache miss samples and adjusts garbage collection object copying heuristics to relocate objects for better cache locality based on those types.

Abstract: Disclosed are a method, apparatus and system for dynamically managing layout of compiled code in a managed runtime environment. Profile feedback is generated during runtime, based on hardware event data that is gathered during runtime. A code manager dynamically relocates compiled code to reduce miss events based on the profile feedback. The code manager may also relocate virtual method tables in a virtual table region in order to reduce data miss events. The method does not require a prior run of an application program because profile feedback is based on event data that is tracked by hardware during execution of the software application and is not based on instrumented code.

Abstract: A compiler or runt-time system may determine a prefetch point to insert an instruction in order to prefetch a memory location and thereby reduce latency in accessing information from a cache. A prefetch predictor generator may decide where and whether to insert the appropriate instructions by looking at information from a hardware monitor. For example, information about cache misses may be analyzed. The differences between target addresses of those cache misses for different instructions may be determined. This information may also be used to determine the locations in the program where the prefetch instructions should be placed, as well as to calculate the address of the memory location being prefetched.

Abstract: We disclose a function unit based finite state automata data structure for use in computer program compilers. According to an aspect of an embodiment, the data structure comprises a function unit vector, having no more used bits than there are issue ports for any particular microprocessor, and a plurality of valid template assignments for each function unit vector. In a preferred embodiment, the template assignments are constructed so as to account for dispersal rules associated with the particular microprocessor. Further, the template assignments can be sorted according to priority data.

Abstract: A compiler comprising an integrated instruction scheduler and resource management system is provided. According to an aspect of an embodiment, the resource management system includes a function unit based finite state automata system. Instructions to be compiled are modeled through the function unit based finite state automata system based on their function unit usage, before they are emitted as compiled computer code. We also disclose a function unit based finite state automata data structure and computer implemented methods for making the same.

Abstract: Disclosed are a method, apparatus and system for dynamically managing layout of compiled code in a managed runtime environment. Profile feedback is generated during runtime, based on hardware event data that is gathered during runtime. A code manager dynamically relocates compiled code to reduce miss events based on the profile feedback. The code manager may also relocate virtual method tables in a virtual table region in order to reduce data miss events. The method does not require a prior run of an application program because profile feedback is based on event data that is tracked by hardware during execution of the software application and is not based on instrumented code.

Abstract: In one embodiment, a method is provided. The method of this embodiment provides reading one or more records event data, the one or more event data corresponding to an event monitored from a system; for each event datum, compressing the event datum if the event datum is determined to be compressible; creating a processed event record, the processed event record conforming to a record format; and storing the one or more event data in the processed event record in accordance with the record format.

Abstract: According to an embodiment of the invention, a method and apparatus are described for memory trace buffering. An embodiment of a processor includes an execution unit and a buffer. The buffer is to store certain data regarding each memory operation of a plurality of memory operations that are executed by the processor.

Abstract: In one embodiment, a method for speculatively reusing regions of code includes identifying a reuse region and a data input to the reuse region, determining whether a data output of the reuse region is contained within reuse region instance information pertaining to a plurality of instances of the reuse region, and when the data output is not contained within the reuse region instance information, predicting the data output of the reuse region based on the reuse region instance information.

Abstract: Methods and apparatus to collect profile information with respect to computer program block(s) are disclosed. A disclosed method collects profile information with respect to target code by predicating execution of profile collection code on a predicate register value; setting the predicate register value to a first predetermined value to permit execution of the profile information collection code to collect profile information with respect to the target code; and setting the predicate register value to a second predetermined value to prevent execution of the profile collection code.

Abstract: We disclose a function unit based finite state automata data structure for use in computer program compilers. According to an aspect of an embodiment, the data structure comprises a function unit vector, having no more used bits than there are issue ports for any particular microprocessor, and a plurality of valid template assignments for each function unit vector. In a preferred embodiment, the template assignments are constructed so as to account for dispersal rules associated with the particular microprocessor. Further, the template assignments can be sorted according to priority data.

Abstract: A compiler comprising an integrated instruction scheduler and resource management system is provided. According to an aspect of an embodiment, the resource management system includes a function unit based finite state automata system. Instructions to be compiled are modeled through the function unit based finite state automata system based on their function unit usage, before they are emitted as compiled computer code. We also disclose a function unit based finite state automata data structure and computer implemented methods for making the same.

Abstract: A method and apparatus that provides instruction re-alignment using a branch on a falsehood of a qualifying predicate. A complementary predicate related to a qualifying predicate is determined to be available. Instructions are re-aligned using a branch on a falsehood of the qualifying predicate if the complementary predicate is not available. Thus, a complementary predicate does not have to be generated to re-align instructions if no complementary predicate is available for the qualifying predicate.

Abstract: The invention is directed to the transformation of software loops having early exit conditions, thereby allowing the loops to be more effectively converted to a single basic block for software pipelining. The invention assigns a predicate register for each early exit condition of the software loop. The predicate registers are set when the corresponding early exit condition is satisfied. In this manner, when the loop terminates the predicate registers can be examined to indicate which early exit conditions were satisfied. The invention produces loops having a lower recurrence II and resource II than conventional techniques.

Abstract: An optimization process is disclosed. The process first finds a parallel compare sequence in a program flow, for example using a flow graph. The guarding predicate (gp) is obtained for the compares. If a new dominating predicate (dp) can be found, the process proceeds to determining if compares for the dp generate the correct or needed initial value for the gp. If there are free result slots available, the proper compares are generated and folded into the initialization. If no free slots are available, it is determined if there is a use of a gp between the dp and gp. If not, the dp is renamed to gp, and the proper compares are generated and folded into the initialization. If there is such a use, the guarding predicate of the compares is found and the process reiterates until it ends with the failure to find a new dominating predicate dp.

Abstract: According to the invention, an apparatus and method are disclosed for configurable system monitoring for dynamic optimization of program execution. According to one embodiment, an event monitoring apparatus for dynamic optimization comprises an event monitor to capture profiles of events that occur in the processing of an application by a microprocessor; an interface to a software component; monitor control vectors to direct the operation of the event monitor; and a profile buffer. According to the embodiment, the events to be monitored are selected by the software component. Profiles of the selected events are captured and stored in the profile buffer. The profiles are made available to a handler routine selected by the software component, which processes the profiles to identify regions of the application for optimization and invokes optimizers to optimize the identified regions.

Abstract: According to the invention, hardware assisted dynamic optimization of program execution is disclosed. According to one embodiment, an application process executed by a microprocessor is optimized by selecting one or more microarchitecture events relating to the execution of the application process to be monitored by one or more hardware monitors; establishing parameters regarding the monitoring of the microarchitecture events by setting one or more monitor control vectors; processing profile data captured by the hardware monitors regarding the occurrence of the microarchitecture events; identifying a region of interest in the application process for optimization based at least in part on the captured profile data; and optimizing the region of interest in the application process.