Abstract: A processor clock generation circuit and related method for a low power consumption modem chip design includes a first clock generator for generating a first clock signal in response to enable and disable signals; a second clock generator for generating a second clock signal that is lower in frequency than the first clock signal; a decoder for decoding an externally inputted instruction to check whether the inputted instruction is a power-down instruction or a power-up instruction, and generating control signals; a clock selection unit for, if the instruction is the power-down instruction, outputting the second clock signal as a processor clock signal and outputting a clock change end signal in response to a control signal outputted from the decoder and, if the instruction is the power-up instruction, outputting the first clock signal as the processor clock signal in response to the outputted control signal from the decoder and a first clock wake-up end signal; and a first clock controller for, if the instruc

Abstract: A method is disclosed for manufacturing a semiconductor device. Initially, a conductive layer is formed over a cell array region, in which high-integrated devices are formed, and over a non-cell region, which functions to assist a proper formation of the cell array region. An etching mask pattern is then formed over the conductive layer to form a conductive pattern over the cell array region and to remove the conductive layer formed on the non-cell region. The conductive pattern is actually formed by etching the conductive layer. An ion-assisted plasma etching is then implemented to form a pattern on the cell array region. This prevents the generation of arcing caused by independent conductive patterns formed on the non-cell region during the ion-assisted plasma etching.

Abstract: A spacer is formed on a side wall of a gate electrode formed over a substrate, and a dielectric interlayer is then formed over the substrate, the gate electrode and the spacer. A region of the dielectric interlayer is then subjected to a first etching process using an etching gas. An emission amount of a chemical compound emitted during the first etching process is detected, where the chemical compound is produced by a chemical reaction of the etching gas and the spacer. The region of the dielectric interlayer is then subjected to a second etching process upon detecting that the emission amount of the chemical compound has reached a given level. The second etching process may be continued until a contact hole is defined in the dielectric interlayer.

Abstract: Disclosed is a processor clock generation circuit and related method for a low power consumption modem chip design, comprising a first clock generator for generating a first clock signal in response to enable and disable signals; a second clock generator for generating a second clock signal that is lower, in frequency, than the first clock signal; a decoder for decoding an externally inputted instruction to check whether the inputted instruction is a power-down instruction or a power-up instruction, and generating control signals; a clock selection unit for, if the instruction is the power-down instruction, outputting the second clock signal as a processor clock signal and outputting a clock change end signal in response to a control signal outputted from the decoder and, if the instruction is the power-up instruction, outputting the first clock signal as the processor clock signal in response to the outputted control signal from the decoder and a first clock wake-up end signal; and a first clock controller f

Abstract: A spacer is formed on a side wall of a gate electrode formed over a substrate, and a dielectric interlayer is then formed over the substrate, the gate electrode and the spacer. A region of the dielectric interlayer is then subjected to a first etching process using an etching gas. An emission amount of a chemical compound emitted during the first etching process is detected, where the chemical compound is produced by a chemical reaction of the etching gas and the spacer. The region of the dielectric interlayer is then subjected to a second etching process upon detecting that the emission amount of the chemical compound has reached a given level. The second etching process may be continued until a contact hole is defined in the dielectric interlayer.

Abstract: A method for etching a metal film containing aluminum, using a hard mask, and a method for forming a line of a semiconductor device using the same, are provided. A metal film containing Al is formed on a semiconductor substrate. A hard mask pattern is formed on the metal film containing Al. Next, the metal film containing Al is etched using an etching gas, including a gas containing carbon, and using the hard mask pattern as the etching mask. Preferably, the hard mask pattern is formed of an oxide film or a nitride film in which case a capping layer for the etched metal layer is not needed.

Abstract: A method of forming a low-k dielectric insulating layer includes forming the dielectric insulating layer and then removing hydrogen bonds in the dielectric insulating layer. The dielectric layer as formed is preferably a HSQ film which contains the structure Si--O--H. Hydrogen is removed from the dielectric layer by either: a heat treatment in plasma, an ozone reduction process, an ion implantation process, or electron beam bombardment.

Abstract: A gas mixture for etching a polysilicon electrode layer in a plasma etching apparatus, and a method for etching the electrode layer using the same. The etching gas mixture is a mixture of Cl.sub.2 gas and N.sub.2 gas, wherein the N.sub.2 gas is in the range of about 30% by volume of the total volume of Cl.sub.2 gas and N.sub.2 gas combined. In the electrode layer etching method of the present invention, the polysilicon electrode layer is formed on a semiconductor substrate. A mask pattern of an oxide or photoresist is then formed on the electrode layer. The electrode layer is etched using a plasma formed by the gas mixture of Cl.sub.2 gas and N.sub.2 gas, with the mask pattern functioning as an etching mask. An upper power source of the plasma etching apparatus delivers power in the range of about 500 to 1000 W, while the etching gas mixture is formed by supplying Cl.sub.2 gas at a rate of about 100 to 400 sccm, and N.sub.2 gas at a rate of about 3 to 15 sccm.

Abstract: An apparatus and a method for measuring both a suspension displacement and a spring force in a vehicle simultaneously measure a suspension displacement and a suspension spring force by attaching a strain gage to a suspension spring. The apparatus for measuring both a suspension displacement and a spring force in a vehicle includes: first to fourth strain gages whose resistance values are varied when a strain is applied thereto; a suspension spring for varying resistances of said strain gages attached thereto; and Wheatstone bridge circuit having a first resistor to fourth resistor, for measuring the suspension displacement and the spring force by using an output voltage to an input voltage which is varied according to a resistance variation outputted from said strain gages.