Abstract: This disclosure describes the structure and technology to modify the free electron density between the gate and drain electrodes of III-nitride semiconductor transistors. Electron density reduction regions (EDR regions) are disposed between the gate and the drain of the transistor structure. In certain embodiments, the EDR regions are created using trenches. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. In another embodiment, a cap layer may be formed in the EDR regions, and doped regions may be created outside of the EDR regions, wherein the impurities act as electron donors.

Abstract: This disclosure describes the structure of a transistor that provides improved performance by reducing the off-state capacitance between the source and the drain by using a cap layer to extend the electrical distance between the gate and the source and drain contacts. In certain embodiments, a dielectric layer may be disposed between the gate electrode and the cap layer and vias are created in the dielectric layer to allow the gate electrode to contact the cap layer at select locations. In some embodiments, the gate electrode is offset from the cap layer to allow a more narrow cap layer and to allow additional space between the gate electrode and the drain contact facilitating the inclusion of a field plate. The gate electrode may be configured to only contact a portion of the cap layer.

Abstract: The structure and technology to improve the device performance of III-nitride semiconductor transistors at high drain voltage when the device is off is disclosed. P-type semiconductor regions are disposed between the gate electrode and the drain contact of the transistor structure. The P-type regions are electrically connected to the drain electrode. In some embodiments, the P-type regions are physically contacting the drain contact. In other embodiments, the P-type regions are physically separate from the drain contact, but electrically connected to the drain contact.

Abstract: This disclosure describes the structure and technology to modify the free electron density between the anode electrode and cathode electrode of III-nitride semiconductor diodes. Electron density reduction regions (EDR regions) are disposed between the anode and cathode electrodes of the diode structure. In certain embodiments, the EDR regions are created using trenches. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. In another embodiment, a cap layer may be formed in the EDR regions, and doped regions may be created outside of the EDR regions, wherein the impurities act as electron donors.

Abstract: This disclosure describes the structure of a transistor that provides improved performance by reducing the off-state capacitance between the source and the drain by using a cap layer to extend the electrical distance between the gate and the source and drain contacts. In certain embodiments, a dielectric layer may be disposed between the gate electrode and the cap layer and vias are created in the dielectric layer to allow the gate electrode to contact the cap layer at select locations. In some embodiments, the gate electrode is offset from the cap layer to allow a more narrow cap layer and to allow additional space between the gate electrode and the drain contact facilitating the inclusion of a field plate. The gate electrode may be configured to only contact a portion of the cap layer.

Abstract: This disclosure describes the structure and technology to modify the free electron density between the gate and drain electrodes of III-nitride semiconductor transistors. Electron density reduction regions (EDR regions) are disposed between the gate and the drain of the transistor structure. In certain embodiments, the EDR regions are created using trenches. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. In another embodiment, a cap layer may be formed in the EDR regions, and doped regions may be created outside of the EDR regions, wherein the impurities act as electron donors.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a plurality of openings in a hardmask material; blocking at least one of the plurality of openings of the hardmask material with a blocking material; etching a skip via to a metallization feature in a stack of metallization features through another of the plurality of openings which is not blocked by the blocking material; and at least partially filling the skip via by a bottom up fill process.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to via and skip via structures and methods of manufacture. The method includes: forming a plurality of openings in a hardmask material; blocking at least one of the plurality of openings of the hardmask material with a blocking material; etching a skip via to a metallization feature in a stack of metallization features through another of the plurality of openings which is not blocked by the blocking material; and at least partially filling the skip via by a bottom up fill process.

Abstract: A method of forming a low dielectric constant (low-k) dielectric is disclosed. The method includes providing a substrate and forming a dielectric including porogens over the substrate. While subjecting the dielectric to a first pressure, the dielectric is exposed to ultraviolet (UV) radiation. The dielectric is also subject to a second pressure less than 1×10?3 Torr. While subjecting the dielectric to the second pressure, the dielectric is exposed to vacuum UV (VUV) radiation having one or more photon energies greater than 7 eV. Since it is difficult for VUV radiation to travel through a medium at a pressure greater than 10 Torr without being absorbed by intermittent materials, subjecting the dielectric to the second pressure creates a medium wherein the dielectric can be exposed to the VUV radiation. By exposing the dielectric to UV and VUV radiation, the dielectric can achieve a reduced dielectric constant and increased mechanical properties.

Abstract: A method of forming a low dielectric constant (low-k) dielectric is disclosed. The method includes providing a substrate and forming a dielectric including porogens over the substrate. While subjecting the dielectric to a first pressure, the dielectric is exposed to ultraviolet (UV) radiation. The dielectric is also subject to a second pressure less than 1×10?3 Torr. While subjecting the dielectric to the second pressure, the dielectric is exposed to vacuum UV (VUV) radiation having one or more photon energies greater than 7 eV. Since it is difficult for VUV radiation to travel through a medium at a pressure greater than 10 Torr without being absorbed by intermittent materials, subjecting the dielectric to the second pressure creates a medium wherein the dielectric can be exposed to the VUV radiation. By exposing the dielectric to UV and VUV radiation, the dielectric can achieve a reduced dielectric constant and increased mechanical properties.