Patents by Inventor Dongjie Tang

Dongjie Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240212258
    Abstract: Examples relate to a caching apparatus, a driver apparatus, a transcoding apparatus and to corresponding devices, methods, and computer programs. The caching apparatus comprises an interface for communicating with one or more cloud gaming instances and processing circuitry that is configured to obtain requests for cached transcoded versions of textures to be used in the one or more cloud gaming instances, and to provide the cached transcoded versions of the textures to the one or more cloud gaming instances.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 27, 2024
    Inventors: Jia BAO, Chao XIE, Yu CHEN, Xiaocheng MAO, Changliang WANG, Yong YAO, Qiming SHI, Dongjie TANG, Hongyu ZHANG
  • Patent number: 11983118
    Abstract: The present disclosure provides a method and apparatus for parsing contiguous system addresses, and an electronic device. The method for parsing contiguous system addresses comprises: acquiring system level information upon receiving contiguous system addresses; acquiring logical address ranges of objects in a first level based on the contiguous system addresses and the system level information; and when successively acquiring logical address ranges of objects in a second level, . . . , or an Nth level of the system, acquiring logical address ranges of objects in a present level based on a logical address range of a previous level and the system level information, wherein N is the number of levels, and N is an integer greater than or equal to 2, and a logical address range of an object comprises a start address and an end address of the object.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 14, 2024
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Qiang Li, Yi Li, Liangliang Niu, Dongjie Tang, Yongjian Lv
  • Publication number: 20220214974
    Abstract: The present disclosure provides a method and apparatus for parsing contiguous system addresses, and an electronic device. The method for parsing contiguous system addresses comprises: acquiring system level information upon receiving contiguous system addresses; acquiring logical address ranges of objects in a first level based on the contiguous system addresses and the system level information; and when successively acquiring logical address ranges of objects in a second level, . . . , or an Nth level of the system, acquiring logical address ranges of objects in a present level based on a logical address range of a previous level and the system level information, wherein N is the number of levels, and N is an integer greater than or equal to 2, and a logical address range of an object comprises a start address and an end address of the object.
    Type: Application
    Filed: December 22, 2021
    Publication date: July 7, 2022
    Applicant: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Qiang LI, Yi LI, Liangliang NIU, Dongjie TANG, Yongjian LV
  • Patent number: 10339333
    Abstract: A method for controlling an application to access a memory includes: receiving a first access request provided by the application and having a first access key; verifying the first access key; generating a second access key for the application if the verification of the first access key is successful; storing the second access key and providing the second access key to the application; receiving a second access request provided by the application and having a target address and a second access key; identifying whether the target address is within a reference address space indicative of a preset storage location of the memory, and verifying the second access key; generating an access control command according to an identification result of whether the target address is within the reference address space and a verification result of the second access key received from the application so as to restrict or permit the application to access the memory.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: July 2, 2019
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Gang Shan, Yi Li, Dongjie Tang
  • Patent number: 10044334
    Abstract: A power amplifier gain attenuation circuit includes: a gain attenuation (reduction) circuit configured to receive an input signal, an external drive signal and a bias voltage, and output a secondary input signal after attenuating the input signal depending on the drive signal and bias voltage; an amplifier including: a bias input terminal configured to receive a bias voltage; a signal input terminal configured to receive a secondary input signal, and an output terminal configured to output a gained output signal. The power amplifier gain attenuation circuit can reduce a gain effectively, and the amount of phase jump caused by the attenuation is quite small.
    Type: Grant
    Filed: December 24, 2017
    Date of Patent: August 7, 2018
    Assignee: LANSUS TECHNOLOGIES INC.
    Inventors: Hua Long, Liyang Zhang, Zhenjuan Cheng, Dongjie Tang, Qian Zhao
  • Patent number: 10044335
    Abstract: A multi-mode multi-band power amplifier includes a controller, a wide-band amplifier channel and a fundamental impedance transformer. The controller receives an external signal and outputs a control signal according to the external signal. The wide-band amplifier channel receives single-band or multi-band RF signals through the input terminal, performs power amplification on the RF signals and outputs the RF signals through the output terminal. The fundamental impedance transformer includes a first segment shared by RF signals in all bands, second segments respectively special for RF signals in all bands, and a switching circuit controlled by the controller to separate RF signals subject to power amplification to the second segment in a switchable manner for multiplexed outputs.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: August 7, 2018
    Assignee: LANSUS TECHNOLOGIES INC.
    Inventors: Hua Long, Liyang Zhang, Zhenjuan Cheng, Dongjie Tang, Qian Zhao
  • Publication number: 20180138880
    Abstract: A power amplifier gain attenuation circuit includes: a gain attenuation (reduction) circuit configured to receive an input signal, an external drive signal and a bias voltage, and output a secondary input signal after attenuating the input signal depending on the drive signal and bias voltage; an amplifier including: a bias input terminal configured to receive a bias voltage; a signal input terminal configured to receive a secondary input signal, and an output terminal configured to output a gained output signal. The power amplifier gain attenuation circuit can reduce a gain effectively, and the amount of phase jump caused by the attenuation is quite small.
    Type: Application
    Filed: December 24, 2017
    Publication date: May 17, 2018
    Applicant: LANSUS TECHNOLOGIES INC.
    Inventors: Hua LONG, Liyang ZHANG, Zhenjuan CHENG, Dongjie TANG, Qian ZHAO
  • Publication number: 20180138881
    Abstract: A power amplifier output power control circuit includes a first operational amplifier with a negative input terminal configured to receive a power control signal; a first PMOS transistor with a grid electrode connected to an output terminal of the first operational amplifier, a source electrode connected to an external power source, and a drain electrode grounded via a voltage dividing network; a power amplifier with a power end connected to the drain electrode of the first PMOS transistor, an input terminal configured to access to a signal to be amplified, and an output terminal configured to amplify the signal; and a current sampling circuit configured to produce sampling current after sampling current across the first PMOS transistor and providing a negative feedback signal for the positive input terminal of the first operational amplifier according to the sampling current such that total output power of the power amplifier keeps unchanged.
    Type: Application
    Filed: December 25, 2017
    Publication date: May 17, 2018
    Applicant: LANSUS TECHNOLOGIES INC.
    Inventors: Hua LONG, Liyang ZHANG, Zhenjuan CHENG, Dongjie TANG, Qian ZHAO
  • Patent number: 9973164
    Abstract: A power amplifier output power control circuit includes a first operational amplifier with a negative input terminal configured to receive a power control signal; a first PMOS transistor with a grid electrode connected to an output terminal of the first operational amplifier, a source electrode connected to an external power source, and a drain electrode grounded via a voltage dividing network; a power amplifier with a power end connected to the drain electrode of the first PMOS transistor, an input terminal configured to access to a signal to be amplified, and an output terminal configured to amplify the signal; and a current sampling circuit configured to produce sampling current after sampling current across the first PMOS transistor and providing a negative feedback signal for the positive input terminal of the first operational amplifier according to the sampling current such that total output power of the power amplifier keeps unchanged.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: May 15, 2018
    Assignee: LANSUS TECHNOLOGIES INC.
    Inventors: Hua Long, Liyang Zhang, Zhenjuan Cheng, Dongjie Tang, Qian Zhao
  • Publication number: 20180123539
    Abstract: A multi-mode multi-band power amplifier includes a controller, a wide-band amplifier channel and a fundamental impedance transformer. The controller receives an external signal and outputs a control signal according to the external signal. The wide-band amplifier channel receives single-band or multi-band RF signals through the input terminal, performs power amplification on the RF signals and outputs the RF signals through the output terminal. The fundamental impedance transformer includes a first segment shared by RF signals in all bands, second segments respectively special for RF signals in all bands, and a switching circuit controlled by the controller to separate RF signals subject to power amplification to the second segment in a switchable manner for multiplexed outputs.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 3, 2018
    Applicant: LANSUS TECHNOLOGIES INC.
    Inventors: Hua LONG, Liyang ZHANG, Zhenjuan CHENG, Dongjie TANG, Qian ZHAO
  • Patent number: 9887679
    Abstract: A power amplifier gain switching circuit includes: a gain controller configured to receive an external input signal, output a first input signal, receive an external drive signal, and output a control signal based on the drive signal; an amplifier including: a bias input terminal configured to receive an external bias voltage; a signal input terminal configured to receive the first input signal; a control terminal configured to receive the control signal; and an output terminal configured to output an output signal with a gain; wherein the amplifier is configured to switch a gain factor of the output signal based on the control signal.
    Type: Grant
    Filed: January 29, 2017
    Date of Patent: February 6, 2018
    Assignee: LANSUS TECHNOLOGIES INC.
    Inventors: Qian Zhao, Liyang Zhang, Hua Long, Zhenjuan Cheng, Dongjie Tang
  • Publication number: 20180025171
    Abstract: A method for controlling an application to access a memory includes: receiving a first access request provided by the application and having a first access key; verifying the first access key; generating a second access key for the application if the verification of the first access key is successful; storing the second access key and providing the second access key to the application; receiving a second access request provided by the application and having a target address and a second access key; identifying whether the target address is within a reference address space indicative of a preset storage location of the memory, and verifying the second access key; generating an access control command according to an identification result of whether the target address is within the reference address space and a verification result of the second access key received from the application so as to restrict or permit the application to access the memory.
    Type: Application
    Filed: December 5, 2016
    Publication date: January 25, 2018
    Inventors: Gang SHAN, Yi LI, Dongjie TANG
  • Publication number: 20170141749
    Abstract: A power amplifier gain switching circuit includes: a gain controller configured to receive an external input signal, output a first input signal, receive an external drive signal, and output a control signal based on the drive signal; an amplifier including: a bias input terminal configured to receive an external bias voltage; a signal input terminal configured to receive the first input signal; a control terminal configured to receive the control signal; and an output terminal configured to output an output signal with a gain; wherein the amplifier is configured to switch a gain factor of the output signal based on the control signal.
    Type: Application
    Filed: January 29, 2017
    Publication date: May 18, 2017
    Applicant: LANSUS TECHNOLOGIES INC.
    Inventors: Qian ZHAO, Liyang ZHANG, Hua LONG, Zhenjuan CHENG, Dongjie TANG
  • Patent number: 9595933
    Abstract: A multi-mode multi-band power amplifier and its circuits are provided. The power amplifier comprises a controller, a wide-band amplifier channel, and a fundamental impedance transformer. The controller receives an external signal and outputs a control signal according to the external signal. The wide-band amplifier channel receives a single-band or a multi-band RF signals through the input terminal, performs power amplification on the RF signals and outputs the RF signals through the output terminal. The fundamental impedance transformer comprises a first segment shared by RF signals in all bands, second segments respectively specific to RF signals in all bands, and a switching circuit controlled by the controller to separate a RF signal which is subject to power amplification to the second segment in a switchable manner for multiplexed outputs. A power amplifier output power control circuit, a gain switching circuit, and a gain attenuation circuit are also provided.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: March 14, 2017
    Assignee: LANSUS TECHNOLOGIES INC.
    Inventors: Qian Zhao, Liyang Zhang, Hua Long, Zhenjuan Cheng, Dongjie Tang
  • Publication number: 20160241213
    Abstract: A multi-mode multi-band power amplifier and its circuits are provided. The power amplifier comprises a controller, a wide-band amplifier channel, and a fundamental impedance transformer. The controller receives an external signal and outputs a control signal according to the external signal. The wide-band amplifier channel receives a single-band or a multi-band RF signals through the input terminal, performs power amplification on the RF signals and outputs the RF signals through the output terminal. The fundamental impedance transformer comprises a first segment shared by RF signals in all bands, second segments respectively specific to RF signals in all bands, and a switching circuit controlled by the controller to separate a RF signal which is subject to power amplification to the second segment in a switchable manner for multiplexed outputs. A power amplifier output power control circuit, a gain switching circuit, and a gain attenuation circuit are also provided.
    Type: Application
    Filed: April 26, 2016
    Publication date: August 18, 2016
    Applicant: LANSUS TECHNOLOGIES INC.
    Inventors: Qian ZHAO, Liyang ZHANG, Hua LONG, Zhenjuan CHENG, Dongjie TANG
  • Publication number: 20070219359
    Abstract: The present invention discloses a pathogenic gene derived from Xanthomonas campestris, a gene encoding phosphoenolpyruvate synthase. The gene encoding phosphoenolpyruvate synthase of this invention has one of the following nucleotide sequence: 1. a nucleotide sequence of SEQ ID NO:1; 2. a DNA sequence which has more than 80% homology with the nucleotide sequence of SEQ ID NO:1, and encodes a protein which has same function as phosphoenolpyruvate synthase encoded by SEQ ID NO:1. The Open Reading Frame of the DNA of SEQ ID NO:1 is from nucleotide 201 to 2576 in its 5? end. It consists of 2379 nucleotides, the initiation codon TTG of this gene is from nucleotides 201 to 203 in its 5? end, and the termination codon TGA of this gene is from nucleotides 2577 to 2579 in its 5? end.
    Type: Application
    Filed: December 1, 2004
    Publication date: September 20, 2007
    Inventors: Jiliang Tang, Yongqiang He, Dongjie Tang, Jiaxun Feng, Baoshan Chen, Guangtao Lu, Bole Jiang, Rongqi Xu