Abstract: A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

Abstract: A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

Abstract: A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

Abstract: A nonvolatile memory device comprises a first mat, a second mat, a third mat, a first address decoder, a second address decoder, and a third address decoder. The first mat comprises first memory blocks, the second mat comprises second memory blocks, and the third mat comprises third memory blocks. The first address decoder selects one of the first memory blocks according to a first even address, the second address decoder selects one of the second memory blocks according to a second even address or a first odd address, and the third address decoder selects one of the third memory blocks according to a second odd address.

Abstract: An erase method of a non-volatile memory device includes first erasing memory cells of a non-volatile memory device with a first erase voltage; in response to a judgment that the erasure of at least one of the memory cells has failed, determining an amount of voltage to add to the first erase voltage, the amount being based on a threshold voltage distribution of the first erased memory cells; and second erasing the memory cells with a second erase voltage, the second erase voltage being higher than the first erase voltage by the determined amount.

Abstract: A nonvolatile memory device comprises a memory cell array comprising memory cells arranged in rows and first columns and flag cells arranged in the rows and second columns. The device further comprises a page buffer configured to read flag data bits from flag cells in a selected row via the second columns, and a judgment unit configured to judge whether memory cells in the selected row are programmed with MSB data based on the flag data bits read by the page buffer.

Abstract: A memory device includes a non-volatile memory core that includes a memory cell array and a page buffer configured to store data to be programmed in the memory cell array. The device also includes a test data input buffer configured to receive test data from an external source, and control circuit that controls the non-volatile memory core and the test data input buffer. The control circuit is configured to load test data from the test data buffer to the page buffer, to program the loaded test data in the page buffer in the memory cell array, and to retain the test data in the page buffer for subsequent programming of the memory cell array. The device may further include a test data output buffer configured to receive data read from the memory cell array, and the control circuit may be operative to convey the read data from the test data output buffer to an external recipient.

Abstract: A nonvolatile memory device comprises a memory cell array comprising memory cells arranged in rows and first columns and flag cells arranged in the rows and second columns. The device further comprises a page buffer configured to read flag data bits from flag cells in a selected row via the second columns, and a judgment unit configured to judge whether memory cells in the selected row are programmed with MSB data based on the flag data bits read by the page buffer.

Abstract: A memory device includes a nonvolatile memory cell array including a plurality of memory cells with a portion of the memory cells to store fuse data, and a fuse register to store the fuse data from the memory cell array. An operation of the memory device is modified in response to the fuse register.

Abstract: A memory device includes a nonvolatile memory cell array including a plurality of memory cells with a portion of the memory cells to store fuse data, and a fuse register to store the fuse data from the memory cell array. An operation of the memory device is modified in response to the fuse register.

Abstract: A memory device includes a non-volatile memory core that includes a memory cell array and a page buffer configured to store data to be programmed in the memory cell array. The device also includes a test data input buffer configured to receive test data from an external source, and control circuit that controls the non-volatile memory core and the test data input buffer. The control circuit is configured to load test data from the test data buffer to the page buffer, to program the loaded test data in the page buffer in the memory cell array, and to retain the test data in the page buffer for subsequent programming of the memory cell array. The device may further include a test data output buffer configured to receive data read from the memory cell array, and the control circuit may be operative to convey the read data from the test data output buffer to an external recipient.

Abstract: A NAND-type flash memory device including a memory cell array having a plurality of memory blocks is provided.

Abstract: A NAND-type flash memory device including a memory cell array having a plurality of memory blocks is provided.