Abstract: An area of on-chip memory is allocated to store one or more tables of commonly-used opcodes. The normal opcode in the instruction is replaced with a shorter code identifying an index into the table. As a result, the instruction is compressed. For a VLIW architecture, in which an instruction includes multiple subinstructions (multiple opcodes), the instruction loading bandwidth is substantially reduced. Preferably, an opcode table is dynamically loaded. Different tasks are programmed with a respective table of opcodes to be stored in the opcode table. The respective table is loaded when task switching.

Abstract: Multi-ported pipelined memory is located on a processor die serving as an addressable on-chip memory for efficiently processing streaming data. The memory sustains multiple wide memory accesses per cycle, clocks synchronously with the rest of the processor, and stores a significant portion of an image. Such memory bypasses the register file directly providing data to the processor's functional units. The memory includes multiple memory banks which permit multiple memory accesses per cycle. The memory banks are connected in pipelined fashion to pipeline registers placed at regular intervals on a global bus. The memory sustains multiple transactions per cycle, at a larger memory density than that of a multi-ported static memory, such as a register file.

Abstract: An accumulation transformation method for fast pattern search accurately locates general patterns of interest. The method can be used for fast invariant search to match patterns of interest in images where the searched pattern varies in size or orientation or aspect ratio, when pattern appearance is degraded, when the pattern is partially occluded, where the searched image is large, multidimensional, or very high resolution, or where the pattern size is large. The accumulation transformations of the input image are determined based upon the searched projection directions. Projection profile result images are derived from the accumulation transformed input image and used for fast matching with template pattern projection profiles.

Abstract: An accumulation method for fast pattern search can accurately locate regular shaped patterns of interest. The method can be used for invariant search to match patterns of interest in images where the searched pattern varies in size or orientation or aspect ratio, when pattern appearance is degraded, and even when the pattern is partially occluded, where the searched image is large, multidimensional, or very high resolution, or where the pattern size is large. The accumulation transformation of the input image is determined based upon the searched pattern. The difference between the accumulation image and a shifted version of itself forms a basic shape pattern image that indicates potential location of the pattern within the input image. The computation requirement is independent of the size of the pattern region.

Abstract: A video processing environment includes a user interface and processing shell from which various video processing ‘plug-in’ programs are accessed. The shell insulates the plug-ins from the intricacies of reading various file formats. The user interface allows an operator to load a video sequence, define and view one or more video objects on any one or more frames of the video sequence, edit existing video object segmentations, view video objects across a series of video frames, and encode video objects among a video sequence in a desired format. Various encoding parameters can be adjusted allowing the operator to view the video sequence encoded at the various parameter settings. The user interface includes a video window, a time-line window, a zoom window, a set of menus including a menu of plug-in programs, and a set of dialogue boxes, including encoding parameter dialogue boxes.

Abstract: Partitioned sigma instructions are provided in which processor capacity is effectively distributed among multiple sigma operations which are executed concurrently. Special registers are included for aligning data on memory word boundaries to reduce packing overhead in providing long data words for multimedia instructions which implement shifting data sequences over multiple iterations. Extended partitioned arithmetic instructions are provided to improve precision and avoid accumulated carry over errors. Partitioned formatting instructions, including partitioned interleave, partitioned compress, and partitioned interleave and compress pack subwords in an effective order for other partitioned operations.

Abstract: A video processing environment includes a user interface and processing shell from which various video processing ‘plug-in’ programs are accessed. The shell insulates the plug-ins from the intricacies of reading various file formats. The user interface allows an operator to load a video sequence, define and view one or more video objects on any one or more frames of the video sequence, edit existing video object segmentations, view video objects across a series of video frames, and encode video objects among a video sequence in a desired format. Various encoding parameters can be adjusted allowing the operator to view the video sequence encoded at the various parameter settings. The user interface includes a video window, a time-line window, a zoom window, a set of menus including a menu of plug-in programs, and a set of dialogue boxes, including encoding parameter dialogue boxes.

Abstract: A learning acceleration method is disclosed that can be applied to multiple types and stages of learning to enhance the learning efficiency and outcome. Artificially created training samples can improve representation of all classes in the training set, decrease the difficulty of obtaining sufficient training samples, and decrease the difficulty of unequal sample prevalence. Two specific embodiments of learning acceleration are disclosed: learning accelerated algorithm training and learning accelerated start-up learning. Three objects of interest implantation methods are disclosed: texture mapping of defects, parametric synthesis of negative samples, and manual image editing.

Abstract: Data are prefetched into a cache from a prefetch region of memory, based on a program instruction reference and on compile-time information that indicates the bounds of the prefetch region, a size of a prefetch block, and a location of the prefetch block. If the program reference address lies with the prefetch region, an offset distance is used to determine the address of the prefetch block. Prefetching is performed either from a continuous one-dimensional prefetch region, or an embedded multi-dimensional prefetch region. The prefetch block address is respectively determined in one dimension or multiple dimensions. Program-directed prefetching is implemented by a media processor or by a separate processing component in communication with the media processor. The primary components include a program-directed prefetch controller, a cache, a function unit, and a memory. Preferably, region registers store the compile-time information, and the prefetched data are stored in a cache prefetch buffer.

Abstract: A programmable graphics pipeline and method for processing multiple partitioned multimedia data, such as graphics data, image data, video data, or audio data. A preferred embodiment of the programmable graphics pipeline includes an instruction cache, a register file, and a vector functional unit that perform partitioned instructions. In addition, an enhanced rasterization unit is used to generate inverse-mapped source coordinates in addition to destination output coordinates for graphics and other media processing. An enhanced texture address unit generates corresponding memory addresses of source texture data for graphics processing and source media data for media processing. Data retrieved from memory are stored in an enhanced texture cache for use by the vector functional unit. A vector output unit includes a blending unit for graphics data and an output buffer for wide media data.

Abstract: A method for efficiently padding a macroblock of a video object plane employs two new instructions. The instructions, PadToRight and PadToLeft, are applied in alternating sequence during a PadPass 1 operation and a PadPass 2 operation. The results of these two operations are then averaged to pad each transparent pixel in each row of a macroblock that includes at least one opaque pixel. A Shift_in register is used to temporarily store data to facilitate the operation implemented by these instructions. Once the transparent pixels in each row have been padded horizontally, pixels in rows having shape data equal to zero (indicating all pixels in the row are transparent) are padded in a pre-processing step, followed by an upward propagation step. The two instructions are preferably implemented using 2:1 multiplexers implemented with an arithmetic logic unit. The method is particularly useful in set-top boxes, games, and other video applications.

Abstract: A boundary macroblock of a video object is padded without significant synchronization overhead between a host processor and an existing coprocessor. The host processor determines horizontal and vertical graphics primitives as a function of shape data stored in a host memory. The shape data determine whether a dot, a line, or a rectangle primitive should be used to pad transparent pixels in the macroblock. The host processor communicates the primitives to a coprocessor, which renders the primitives in an interleaved pipeline fashion to pad transparent pixels of the macroblock based on texture data stored in video memory. The flow of primitives is in one direction from the host processor to the graphics coprocessor, and the texture data is not transferred back and forth between the host processor and coprocessor. This technique is especially useful for enabling acceleration of MPEG-4 video decoding utilizing existing coprocessors capable of accelerating MPEG-1/2 video decoding.

Abstract: A video processing environment includes a user interface and processing shell from which various video processing ‘plug-in’ programs are accessed. The shell insulates the plug-ins from the intricacies of reading various file formats. The user interface allows an operator to load a video sequence, define and view one or more video objects on any one or more frames of the video sequence, edit existing video object segmentations, view video objects across a series of video frames, and encode video objects among a video sequence in a desired format. Various encoding parameters can be adjusted allowing the operator to view the video sequence encoded at the various parameter settings. The user interface includes a video window, a time-line window, a zoom window, a set of menus including a menu of plug-in programs, and a set of dialogue boxes, including encoding parameter dialogue boxes.

Abstract: A video processing environment includes a user interface and processing shell from which various video processing ‘plug-in’ programs are accessed. The shell insulates the plug-ins from the intricacies of reading various file formats. The user interface allows an operator to load a video sequence, define and view one or more video objects on any one or more frames of the video sequence, edit existing video object segmentations, view video objects across a series of video frames, and encode video objects among a video sequence in a desired format. Various encoding parameters can be adjusted allowing the operator to view the video sequence encoded at the various parameter settings. The user interface includes a video window, a time-line window, a zoom window, a set of menus including a menu of plug-in programs, and a set of dialogue boxes, including encoding parameter dialogue boxes.

Abstract: Multi-ported pipelined memory is located on a processor die serving as an addressable on-chip memory for efficiently processing streaming data. The memory sustains multiple wide memory accesses per cycle, clocks synchronously with the rest of the processor, and stores a significant portion of an image. Such memory bypasses the register file directly providing data to the processor's functional units. The memory includes multiple memory banks which permit multiple memory accesses per cycle. The memory banks are connected in pipelined fashion to pipeline registers placed at regular intervals on a global bus. The memory sustains multiple transactions per cycle, at a larger memory density than that of a multi-ported static memory, such as a register file.