Abstract: A conductive material dispersion liquid, and an electrode and a lithium secondary battery manufactured using the same. The conductive material dispersion liquid includes a carbon-based conductive material, a dispersant, and a dispersion medium. The dispersant is a copolymer including a first repeating unit represented by Chemical Formula 1, a second repeating unit represented by Chemical Formula 2, and a third repeating unit represented by Chemical Formula 3, and the dispersion medium is a non-aqueous solvent.

Abstract: The present disclosure relates to a secondary battery manufacturing system having a multi-packaging unit, in which multiple packaging units of a secondary battery manufacturing facility are provided and a transfer box on which an electrode assembly is accommodated is transferred to each packaging unit by a transfer unit, wherein the secondary battery manufacturing system includes: an electrode supply unit equipped with a plurality of stacking devices for supplying an electrode assembly in which a plurality of battery cells are stacked; a tab-welding unit; at least one packaging unit; at least one temporary buffer; and a transfer unit.

Abstract: Disclosed is a cushion tip-up type seat for a vehicle. The cushion tip-up type seat for a vehicle is configured to perform a tip-up function of a cushion part, and to move a seat leftward and rightward to adjust an interval between left and right seats, whereby left and right spacing between occupants seated in the seats is sufficiently secured and the convenience of the occupants is improved.

Abstract: An image sensor includes a plurality of unit pixels, each including: a substrate including first and second sides which are opposite to each other, a photoelectric conversion layer in the substrate, and a wiring structure on the first side of the substrate. The wiring structure may include: a first capacitor, a second capacitor spaced from the first capacitor, a plurality of edge vias arranged along edges of the unit pixel, and a plurality of central vias interposed between the first capacitor and the second capacitor.

Abstract: The present disclosure relates to a secondary battery manufacturing system in which a packaging unit of a secondary battery manufacturing facility are configured to have multiple packaging units, and having a multipackaging unit such that a transfer box in which an electrode assembly is seated is transferred to each of the packaging units by a transfer unit, and including an electrode supply unit having a plurality of stacking devices supplying an electrode assembly in which a plurality of battery cells are stacked, a tab welding unit, at least one packaging unit, at least one temporary buffer, and a transfer unit.

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

Abstract: A semiconductor device includes a monitoring circuit receiving a first supply signal and generating a flag signal by monitoring a second supply signal provided to a monitored circuit; a watchdog circuit disposed in the monitoring circuit, receiving the first supply signal, and generating a watchdog signal; and a comparison circuit receiving the flag signal and the watchdog signal and generating a first signal which has a first level under an abnormal condition and a second level under a normal condition. The second level is different than the first level. The watchdog circuit sets the watchdog signal to a third level when the level of the first supply signal is lower than a first reference level. When the watchdog signal has the third level, the comparison circuit allows the first signal to have the first level regardless of the level of the flag signal.

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

Abstract: A periodic process performing system includes a system processor to which a first periodic real-time process, which starts to be executed starts for each of a first time interval from a first start time, is assigned; a wakeup logic which provides the system processor with a first state capable of executing the first periodic real-time process; and a counter which supplies a first tick signal to the wakeup logic for each of the first time interval from a second start time earlier than the first start time, and supplies a second tick signal to the system processor for each of the first time interval from a third start time between the first start time and the second start time.

Abstract: A subsystem interface, a semiconductor device including the subsystem interface, and a communications method of the semiconductor device are provided, the subsystem interface comprising a transmitter including a first transmission port configured to transmit a first clock signal, a second transmission port configured to transmit a first data signal, a first reception port configured to receive a first flow control signal, and a third transmission port configured to transmit a first synchronization signal, a receiver including a second reception port configured to receive a second clock signal, a third reception port configured to receive a second data signal, a fourth transmission port configured to transmit a second flow control signal, a fourth reception port configured to receive a second synchronization signal, and a control module configured to control operations of the transmitter and the receiver, including performing a transmitter hand-shake by sending a request signal from the second transmission por

Abstract: An apparatus includes a first function module providing a master signal, a second function module providing a comparison signal, and safety logic. The safety logic includes a toggle signal generator having a comparator providing a comparison result in response to the master signal and the comparison signal, a feedback path generating a first toggle signal in response to the comparison result and providing a feedback signal to the comparator, and a first multiple input gate generating a second toggle signal in response to the comparison result. The safety logic also includes a toggle signal monitor providing a final fault search signal in response to the first toggle signal and the second toggle signal.

Abstract: An apparatus includes a first function module providing a master signal, a second function module providing a comparison signal, and safety logic. The safety logic includes a toggle signal generator having a comparator providing a comparison result in response to the master signal and the comparison signal, a feedback path generating a first toggle signal in response to the comparison result and providing a feedback signal to the comparator, and a first multiple input gate generating a second toggle signal in response to the comparison result. The safety logic also includes a toggle signal monitor providing a final fault search signal in response to the first toggle signal and the second toggle signal.

Abstract: An apparatus includes a first function module providing a master signal, a second function module providing a comparison signal, and safety logic. The safety logic includes a toggle signal generator having a comparator providing a comparison result in response to the master signal and the comparison signal, a feedback path generating a first toggle signal in response to the comparison result and providing a feedback signal to the comparator, and a first multiple input gate generating a second toggle signal in response to the comparison result. The safety logic also includes a toggle signal monitor providing a final fault search signal in response to the first toggle signal and the second toggle signal.

Abstract: A semiconductor device includes a monitoring circuit receiving a first supply signal and generating a flag signal by monitoring a second supply signal provided to a monitored circuit; a watchdog circuit disposed in the monitoring circuit, receiving the first supply signal, and generating a watchdog signal; and a comparison circuit receiving the flag signal and the watchdog signal and generating a first signal which has a first level under an abnormal condition and a second level under a normal condition. The second level is different than the first level. The watchdog circuit sets the watchdog signal to a third level when the level of the first supply signal is lower than a first reference level. When the watchdog signal has the third level, the comparison circuit allows the first signal to have the first level regardless of the level of the flag signal.

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

Abstract: An apparatus includes a first function module providing a master signal, a second function module providing a comparison signal, and safety logic. The safety logic includes a toggle signal generator having a comparator providing a comparison result in response to the master signal and the comparison signal, a feedback path generating a first toggle signal in response to the comparison result and providing a feedback signal to the comparator, and a first multiple input gate generating a second toggle signal in response to the comparison result. The safety logic also includes a toggle signal monitor providing a final fault search signal in response to the first toggle signal and the second toggle signal.

Abstract: A method of scheduling a system-on-chip (SoC) by a scheduler, located between a plurality of masters and a slave, includes receiving a plurality of access requests from the plurality of masters, setting the plurality of access requests in a plurality of registers, and scheduling the plurality of access requests based on the plurality of access requests.

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.