Patents by Inventor Dongyang Tang
Dongyang Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240176574Abstract: An integrated circuit is provided with a terminal that functions to pass a data signal during a high-speed data mode of operation and to pass an audio signal during an audio mode of operation. The integrated circuit includes an audio source that couples to the terminal through an audio pass transistor during the audio mode of operation. To maintain the audio pass transistor off during the high-speed data mode of operation, the integrated circuit includes a first transistor coupled between the terminal and a gate of the audio pass transistor. The first transistor conducts negative charge from the terminal to the gate of the audio pass transistor.Type: ApplicationFiled: November 30, 2022Publication date: May 30, 2024Inventors: Dongyang TANG, Ramkumar SIVAKUMAR, Khaled Mahmoud ABDELFATTAH ALY
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Publication number: 20240178663Abstract: An ESD trigger circuit is provided for protecting a pass transistor coupled to an integrated circuit terminal. The integrated circuit terminal couples through a diode to a voltage node. In response to an electrostatic shock at the integrated circuit terminal, the diode conducts charge to the voltage node to pulse a voltage of the voltage node. The ESD trigger circuit responds to the pulse of the voltage by coupling the voltage node to a gate of the pass transistor.Type: ApplicationFiled: November 28, 2022Publication date: May 30, 2024Inventors: Kshitij YADAV, Vijayakumar DHANASEKARAN, Khaled Mahmoud ABDELFATTAH ALY, Ramkumar SIVAKUMAR, Dongyang TANG, Chienchung YANG
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Publication number: 20240162874Abstract: A transmission line includes an equalization circuit. The equalization circuit is a second-order equalization circuit having a first loop at a gain element and a second loop at the gain element. The first loop may include a first compensation capacitor, and the second loop may include a second compensation capacitor and a resistor. The second order equalization circuit may allow for improved performance with respect to gain as well as reduced power usage.Type: ApplicationFiled: November 16, 2022Publication date: May 16, 2024Inventors: Dongyang TANG, Ramkumar SIVAKUMAR, Khaled Mahmoud ABDELFATTAH ALY, Vijayakumar DHANASEKARAN
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Publication number: 20240111956Abstract: Disclosed are a Nested Named Entity Recognition method based on part-of-speech awareness, system, device and storage medium therefor. The method uses a BiLSTM model to extract a feature of text word data in order to obtain a text word depth feature, and each text word of text to be recognized is initialized into a corresponding graph node, and a text heterogeneous graph of the text to be recognized is constructed according to a preset part-of-speech path, the text word data of the graph nodes is updated by an attention mechanism, and the features of all graph nodes of the text heterogeneous graph are extracted using the BiLSTM model, and a nested named entity recognition result is obtained after decoding and annotating. The present disclosure can recognize ordinary entities and nested entities accurately and effectively, and enhance the performance and advantages of the nested named entity recognition model.Type: ApplicationFiled: November 28, 2023Publication date: April 4, 2024Inventors: Jing Qiu, Ling Zhou, Chengliang Gao, Rongrong Chen, Ximing Chen, Zhihong Tian, Lihua Yin, Hui Lu, Yanbin Sun, Junjun Chen, Dongyang Zheng, Fei Tang, Jiaxu Xing
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Publication number: 20230238925Abstract: Aspects of the present disclosure relate to apparatus and methods for dynamically adjusting the common-mode input signal of a power amplifier, such as a class-D power amplifier. One example power amplifier circuit generally includes a first amplifier having a signal input and a power input; and a common-mode adjustment circuit having a first input coupled to the power input of the first amplifier, having an output coupled to the signal input of the first amplifier, and being configured to generate a common-mode signal to apply to the signal input of the first amplifier, based on a power supply voltage on the power input of the first amplifier.Type: ApplicationFiled: January 26, 2022Publication date: July 27, 2023Inventors: Dongyang TANG, Xinwang ZHANG, ChienChung YANG, Earl SCHREYER, Sherif GALAL
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Patent number: 11683015Abstract: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.Type: GrantFiled: August 17, 2021Date of Patent: June 20, 2023Assignee: QUALCOMM IncorporatedInventors: ChienChung Yang, Dongyang Tang, Sherif Galal, Xinwang Zhang, Subbarao Surendra Chakkirala, Pradeep Silva
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Publication number: 20230058434Abstract: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.Type: ApplicationFiled: August 17, 2021Publication date: February 23, 2023Inventors: ChienChung YANG, Dongyang TANG, Sherif GALAL, Xinwang ZHANG, Subbarao Surendra CHAKKIRALA, Pradeep SILVA
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Patent number: 11424720Abstract: A power amplifier provides reduction of click and pop in audio applications. The power amplifier includes a first amplifier and an auxiliary amplifier. The auxiliary amplifier is used to ramp the power amplifier output from ground to an offset voltage to reduce the “click and pop” sound. The first amplifier and the auxiliary amplifier having a shared feedback loop. An output of the first amplifier and an output of the auxiliary amplifier may be switchably coupled to the shared feedback loop. A wave generator controls a switch to couple the first amplifier output or the auxiliary amplifier output to the shared feedback loop.Type: GrantFiled: March 23, 2020Date of Patent: August 23, 2022Assignee: QUALCOMM IncorporatedInventors: Pradeep Silva, Ramkumar Sivakumar, Qubo Zhou, Xinwang Zhang, Hanil Lee, Dongyang Tang, Vijayakumar Dhanasekaran
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Publication number: 20220263471Abstract: An apparatus is disclosed for reducing resistor conductivity modulation during amplification. In an example aspect, the apparatus includes a power amplifier circuit comprising a first pair of resistors, a digital-to-analog converter comprising a second pair of resistors, a reference generation circuit comprising a third pair of resistors, and a scaling circuit. The scaling circuit is configured to accept a common-mode reference voltage and a common-mode output voltage. The scaling circuit is also configured to provide a first voltage at body terminals of the first pair of resistors, a second voltage at body terminals of the second pair of resistors, and a third voltage at body terminals of the third pair of resistors such that a summation of the first voltage and the third voltage reduced by the second voltage is approximately equal to an average of the common-mode reference voltage and the common-mode output voltage.Type: ApplicationFiled: August 22, 2019Publication date: August 18, 2022Inventors: Khaled Mahmoud Abdelfattah Aly, Chaoli Zhong, Dongyang Tang
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Publication number: 20210297046Abstract: A power amplifier provides reduction of click and pop in audio applications. The power amplifier includes a first amplifier and an auxiliary amplifier. The auxiliary amplifier is used to ramp the power amplifier output from ground to an offset voltage to reduce the “click and pop” sound. The first amplifier and the auxiliary amplifier having a shared feedback loop. An output of the first amplifier and an output of the auxiliary amplifier may be switchably coupled to the shared feedback loop. A wave generator controls a switch to couple the first amplifier output or the auxiliary amplifier output to the shared feedback loop.Type: ApplicationFiled: March 23, 2020Publication date: September 23, 2021Inventors: Pradeep SILVA, Ramkumar SIVAKUMAR, Qubo ZHOU, Xinwang ZHANG, Hanil LEE, Dongyang TANG, Vijayakumar DHANASEKARAN
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Patent number: 10673449Abstract: A digital-to-analog converter has both a plurality of DAC stages and a plurality of dummy stages. Each DAC stage causes a glitch or disturbance to a pair of reference voltages when the DAC stage changes its switching state. Each dummy stage also causes a similar glitch or disturbance to the pair of reference voltages when the dummy stage changes its switching state. The dummy stages are controlled to change their switching state responsive to how many DAC stages change their switching state such that a total glitch induced onto the reference voltages remains substantially constant across a succession of digital words converted by the digital-to-analog converter into an analog output signal.Type: GrantFiled: April 30, 2019Date of Patent: June 2, 2020Assignee: QUALCOMM IncorporatedInventors: Chien-Chung Yang, Dongyang Tang, Vijayakumar Dhanasekaran
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Patent number: 10447212Abstract: An apparatus includes a reference voltage circuit having a bandgap input and a reference voltage output. The apparatus also includes a digital-to-analog converter (DAC) coupled to the reference voltage output and having a digital signal input. The apparatus includes an amplifier having a first input coupled to an output of the DAC. The first input is coupled to an output of the amplifier via a feedback resistor. The apparatus includes a resistor coupled to the reference voltage output and having a body terminal coupled to the output of the amplifier.Type: GrantFiled: May 22, 2018Date of Patent: October 15, 2019Assignee: QUALCOMM IncorporatedInventors: Arash Mehrabi, Zongyu Dong, Vijayakumar Dhanasekaran, Dongyang Tang, Chien-Chung Yang
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Publication number: 20180269839Abstract: An apparatus includes a reference voltage circuit having a bandgap input and a reference voltage output. The apparatus also includes a digital-to-analog converter (DAC) coupled to the reference voltage output and having a digital signal input. The apparatus includes an amplifier having a first input coupled to an output of the DAC. The first input is coupled to an output of the amplifier via a feedback resistor. The apparatus includes a resistor coupled to the reference voltage output and having a body terminal coupled to the output of the amplifier.Type: ApplicationFiled: May 22, 2018Publication date: September 20, 2018Inventors: Arash Mehrabi, Zongyu Dong, Vijayakumar Dhanasekaran, Dongyang Tang, Chien-Chung Yang
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Patent number: 9998077Abstract: An apparatus includes an amplifier having a first input and a second input. A first feedback resistor is coupled to the first input and has a first body terminal coupled to a first bias terminal. A second feedback resistor is coupled to the second input and has a second body terminal coupled to a second bias terminal.Type: GrantFiled: June 21, 2016Date of Patent: June 12, 2018Assignee: QUALCOMM IncorporatedInventors: Arash Mehrabi, Zongyu Dong, Vijayakumar Dhanasekaran, Dongyang Tang, Chien-Chung Yang
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Publication number: 20170187336Abstract: An apparatus includes an amplifier having a first input and a second input. A first feedback resistor is coupled to the first input and has a first body terminal coupled to a first bias terminal. A second feedback resistor is coupled to the second input and has a second body terminal coupled to a second bias terminal.Type: ApplicationFiled: June 21, 2016Publication date: June 29, 2017Inventors: Arash Mehrabi, Zongyu Dong, Vijayakumar Dhanasekaran, Dongyang Tang, Chien-Chung Yang
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Publication number: 20170063368Abstract: Certain aspects of the present disclosure provide methods and apparatus for setting a voltage level for controlling at least one of a first switch or a second switch, such that an on-resistance of the first switch matches an on-resistance of the second switch. One example circuit generally includes a third switch configured to replicate the first switch and a first cascode device connected in cascode with the third switch; a first amplifier configured to drive the first cascode device; a fourth switch configured to replicate the second switch; a second cascode device connected in cascode with the fourth switch; a second amplifier configured to drive the second cascode device; and a third amplifier configured to compare a voltage at a node coupled to the first and second cascode devices with a reference potential and to control the third switch based on the comparison to set the voltage level.Type: ApplicationFiled: August 25, 2015Publication date: March 2, 2017Inventors: Dongyang TANG, Vijayakumar DHANASEKARAN
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Publication number: 20170054415Abstract: A voltage reference buffer circuit, including: an amplifier having input terminals and output terminals; a plurality of current sources coupled to the input terminals of the amplifier, the plurality of current sources including a plurality of degeneration resistors coupled to a first plurality of voltage supplies; and a degeneration resistor chopping module comprising a first and second plurality of switches coupled to the plurality of degeneration resistors.Type: ApplicationFiled: August 19, 2015Publication date: February 23, 2017Inventors: Dongyang Tang, Vijayakumar Dhanasekaran