Patents by Inventor Donia Sebastian
Donia Sebastian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240094939Abstract: Systems and methods are provided for dynamically changing the operating clock frequency of a circuit. Control circuitry determines a first workload value for a circuit operating at a first clock frequency. Control circuitry then detect a second workload value for the circuit, which is less than the first workload value. When the control circuitry detects the second workload value, the control circuitry calculates a second clock frequency which is greater than the first clock frequency. The control circuitry then causes the circuit to operate at the second clock frequency.Type: ApplicationFiled: September 20, 2022Publication date: March 21, 2024Inventors: David J. Pelster, Donia Sebastian
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Patent number: 11914899Abstract: A system (e.g., NVMe controller) for managing access to a memory resource by multiple users may include memory storing function queue categorizations for function queues associated with each user, and circuitry to store and execute a multi-user arbitration algorithm that arbitrates access to the memory resource by the multiple users. The function queue categorizations assign a function category to each function queue associated with each user.Type: GrantFiled: May 13, 2022Date of Patent: February 27, 2024Assignee: Microchip Technology IncorporatedInventors: Kwok Kong, William Brent Wilson, Ihab Jaser, Donia Sebastian, Dan McLeran
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Publication number: 20240020013Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.Type: ApplicationFiled: September 27, 2023Publication date: January 18, 2024Inventors: David J. Pelster, Yogesh B. Wakchaure, Neelesh Vemula, Aliasgar S. Madraswala, David B. Carlton, Donia Sebastian, Mark Anthony Golez, Xin Guo
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Patent number: 11797188Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.Type: GrantFiled: December 12, 2019Date of Patent: October 24, 2023Assignee: SK hynix NAND Product Solutions Corp.Inventors: David J. Pelster, Yogesh B. Wakchaure, Neelesh Vemula, Aliasgar S. Madraswala, David B. Carlton, Donia Sebastian, Mark Anthony Golez, Xin Guo
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Publication number: 20230135952Abstract: A system (e.g., NVMe controller) for managing access to a memory resource by multiple users may include memory storing function queue categorizations for function queues associated with each user, and circuitry to store and execute a multi-user arbitration algorithm that arbitrates access to the memory resource by the multiple users. The function queue categorizations assign a function category to each function queue associated with each user.Type: ApplicationFiled: May 13, 2022Publication date: May 4, 2023Applicant: Microchip Technology IncorporatedInventors: Kwok Kong, William Brent Wilson, Ihab Jaser, Donia Sebastian, Dan McLeran
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Publication number: 20230115296Abstract: An apparatus and method for scheduling memory requests including receiving a plurality of requests having a type and associating each request of the received plurality of requests with a corresponding target, which is associated with one channel of a plurality of channels. The method assigning a priority to each request, assigning a utilization cost to each request based on the request’s target and request type, and queueing each request of the plurality of requests for scheduling. The method selecting a first request of the received plurality of requests to be scheduled based on its priority, scheduling the first request for processing at a time when the first request utilization cost is less than or equal to a current value of a dynamic utilization counter, and debiting the dynamic utilization counter by the first request utilization cost.Type: ApplicationFiled: September 6, 2022Publication date: April 13, 2023Applicant: Microchip Technology IncorporatedInventors: Ihab Jaser, Jack Wynne, Kwok Kong, Donia Sebastian, Xin Guo
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Publication number: 20220083419Abstract: Systems, apparatuses and methods may provide for technology that generates a first set of scrambler bits based on a destination page number associated with data, generates a second set of scrambler bits based on a programmable nonlinear function, and combines the first set of scrambler bits and the second set of scrambler bits into a scrambler seed. In one example, the technology also randomizes the data based on the scrambler seed to obtain outgoing randomized data and writes the outgoing randomized data to a non-volatile memory.Type: ApplicationFiled: November 24, 2021Publication date: March 17, 2022Inventors: Xin Guo, Ravi Motwani, Donia Sebastian, Aaron Lutzker
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Patent number: 10877696Abstract: Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.Type: GrantFiled: March 28, 2019Date of Patent: December 29, 2020Assignee: Intel CorporationInventors: Yogesh B. Wakchaure, Aliasgar S. Madraswala, David J. Pelster, Donia Sebastian, Curtis Gittens, Xin Guo, Neelesh Vemula, Varsha Regulapati, Naga Kiranmayee Upadhyayula
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Patent number: 10789124Abstract: Examples described herein can be used to reduce a number of re-read operations and potentially avoid data recovery operations, which can be time consuming. A determination can be made of a read voltage to apply during an operation to cause a read of data stored in a region of a memory device. The region of the memory device can be read using the read voltage. If the region is not successfully read, then an error level indication can be measured and a second read voltage can be determined for a re-read operation. If the re-read operation is not successful, then a second error level indication can be measured for the re-read operation. A third read voltage can be selected based on the change from the error level indication to the second error level indication.Type: GrantFiled: September 28, 2018Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Lei Chen, Xin Guo, Shu-Jen Lee, Chu-hsiang Teng, Scott Nelson, Donia Sebastian
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Publication number: 20200117369Abstract: A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.Type: ApplicationFiled: December 12, 2019Publication date: April 16, 2020Inventors: David J. PELSTER, Yogesh B. WAKCHAURE, Neelesh VEMULA, Aliasgar S. MADRASWALA, David B. CARLTON, Donia SEBASTIAN, Mark Anthony GOLEZ, Xin GUO
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Patent number: 10453540Abstract: A reduction in Quality of Service (QoS) latency for host read commands in a power limited operation mode in a storage device is provided. A priority level is assigned to a host command using weighted round robin arbitration. Power resources are allocated based on the priority levels assigned to host commands to minimize host read command latency in the power limited operation mode.Type: GrantFiled: April 23, 2018Date of Patent: October 22, 2019Assignee: Intel CorporationInventors: Xin Guo, Yu Du, Curtis Gittens, David J. Pelster, Donia Sebastian
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Publication number: 20190227749Abstract: Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.Type: ApplicationFiled: March 28, 2019Publication date: July 25, 2019Inventors: Yogesh B. WAKCHAURE, Aliasgar S. MADRASWALA, David J. PELSTER, Donia SEBASTIAN, Curtis GITTENS, Xin GUO, Neelesh VEMULA, Varsha REGULAPATI, Naga Kiranmayee UPADHYAYULA
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Publication number: 20190043593Abstract: A reduction in Quality of Service (QoS) latency for host read commands in a power limited operation mode in a storage device is provided. A priority level is assigned to a host command using weighted round robin arbitration. Power resources are allocated based on the priority levels assigned to host commands to minimize host read command latency in the power limited operation mode.Type: ApplicationFiled: April 23, 2018Publication date: February 7, 2019Inventors: Xin GUO, Yu DU, Curtis GITTENS, David J. PELSTER, Donia SEBASTIAN
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Publication number: 20190042130Abstract: A system for reconfiguring flash memory from a default access operation mode (e.g., MLC, TLC, or QLC mode) to a non-default access operation mode (e.g., SLC mode) using opcode prefixes is provided. Opcode prefix logic enables the flash memory die to enter a non-default (e.g., faster) access operation mode. The non-default access operation mode is entered by providing a prefix instruction or opcode prefix to the memory controller and/or to the flash memory die prior to memory operation commands (“opcode”) for program, read, and/or erase. The flash memory die is configured to automatically exit the non-default access operation mode after a single operation, or the flash memory die is configured to exit the non-default access operation mode upon receipt of another opcode prefix.Type: ApplicationFiled: December 18, 2017Publication date: February 7, 2019Applicant: Intel CorporationInventors: NAVEEN VITTAL PRABHU, ALIASGAR S. MADRASWALA, DONIA SEBASTIAN, SHANKAR NATARAJAN
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Publication number: 20190042356Abstract: Examples described herein can be used to reduce a number of re-read operations and potentially avoid data recovery operations, which can be time consuming. A determination can be made of a read voltage to apply during an operation to cause a read of data stored in a region of a memory device. The region of the memory device can be read using the read voltage. If the region is not successfully read, then an error level indication can be measured and a second read voltage can be determined for a re-read operation. If the re-read operation is not successful, then a second error level indication can be measured for the re-read operation. A third read voltage can be selected based on the change from the error level indication to the second error level indication.Type: ApplicationFiled: September 28, 2018Publication date: February 7, 2019Inventors: Lei CHEN, Xin GUO, Shu-Jen LEE, Chu-hsiang TENG, Scott NELSON, Donia SEBASTIAN
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Patent number: 10109361Abstract: A memory programmer apparatus may include a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass, a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion, and a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.Type: GrantFiled: June 29, 2017Date of Patent: October 23, 2018Assignee: Intel CorporationInventors: Ali Khakifirooz, Pranav Kalavade, Rohit S. Shenoy, Aliasgar S. Madraswala, Donia Sebastian, Xin Guo
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Patent number: 10095432Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.Type: GrantFiled: July 21, 2017Date of Patent: October 9, 2018Assignee: Intel CorporationInventors: Donia Sebastian, Simon D. Ramage, Curtis A. Gittens, Scott Nelson, David B. Carlton, Kai-Uwe Schmidt
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Publication number: 20180101323Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.Type: ApplicationFiled: July 21, 2017Publication date: April 12, 2018Applicant: Intel CorporationInventors: Donia Sebastian, Simon D. Ramage, Curtis A. Gittens, Scott Nelson, David B. Carlton, Kai-Uwe Schmidt
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Patent number: 9727267Abstract: In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the command may be dynamically allocated, wherein power for a first stage of the command is allocated first, and power for each remaining stage of the command is allocated after a preceding stage is performed.Type: GrantFiled: September 27, 2016Date of Patent: August 8, 2017Assignee: Intel CorporationInventors: Donia Sebastian, Simon D. Ramage, Curtis A. Gittens, Scott Nelson, David B. Carlton, Kai-Uwe Schmidt
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Publication number: 20160283111Abstract: Apparatus, systems, and methods to implement read operations in nonvolatile memory devices are described. In one example, a controller comprises logic to receive a first read request from a host device, place the first read request in a read queue comprising a plurality of read requests directed to the nonvolatile memory, determine a first target die and a first target plane in the nonvolatile memory for the first read request and combine the first read request with at least a second read request in the read queue to form a combined read request, wherein the second read request comprise a second target die, which is the same as the first target die, and a second target plane which is different from the first target plane. Other examples are also disclosed and claimed.Type: ApplicationFiled: March 26, 2015Publication date: September 29, 2016Applicant: Intel CorporationInventors: Xin Guo, David B. Carlton, Scott Nelson, David J. Pelster, Donia Sebastian