Patents by Inventor Doorlabh Panjwani

Doorlabh Panjwani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11193953
    Abstract: Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: December 7, 2021
    Assignee: International Business Machines Corporation
    Inventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou
  • Publication number: 20190265273
    Abstract: Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.
    Type: Application
    Filed: May 10, 2019
    Publication date: August 29, 2019
    Inventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou
  • Patent number: 10371717
    Abstract: Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou
  • Publication number: 20170336440
    Abstract: Structures and methods for directly testing a semiconductor wafer having micro-solder connections. According to one embodiment, a method forms a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer. According to another embodiment, a method tests the pattern of micro-solder connections. According to another embodiment, a novel electrical probe tip structure has contacts on the same pitch as the pattern of micro-solder connections.
    Type: Application
    Filed: August 8, 2017
    Publication date: November 23, 2017
    Inventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou
  • Patent number: 9726691
    Abstract: The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having micro-solder connections. According to one embodiment of the present invention, a method of forming a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer, is disclosed. According to another embodiment, a method of testing the pattern of micro-solder connections is disclosed. According to another embodiment, a novel electrical probe tip structure, having contacts on the same pitch as the pattern of micro-solder connections is disclosed.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou
  • Publication number: 20170177178
    Abstract: Provided are techniques for capturing and displaying context information associated with a displayed document, comprising identifying a first plurality of words within a displayed document; applying natural language processing (NPL) to text in proximity to the first plurality of words in the document to identify a first context sensitive usage corresponding to the first plurality of words; storing a reference to the first plurality of words in conjunction with the first context sensitive usage; and in response to a user selection of the first plurality of words, displaying the first context sensitive usage in conjunction with the first plurality of words.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Applicant: International Business Machines Corporation
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Doorlabh Panjwani
  • Publication number: 20170177179
    Abstract: Provided are techniques for capturing and displaying context information associated with a displayed document, comprising identifying a first plurality of words within a displayed document; applying natural language processing (NPL) to text in proximity to the first plurality of words in the document to identify a first context sensitive usage corresponding to the first plurality of words; storing a reference to the first plurality of words in conjunction with the first context sensitive usage; and in response to a user selection of the first plurality of words, displaying the first context sensitive usage in conjunction with the first plurality of words.
    Type: Application
    Filed: March 22, 2016
    Publication date: June 22, 2017
    Applicant: International Business Machines Corporation
    Inventors: Victor A. Garibay, Daniel E. Hurlimann, Chetan Mehta, Doorlabh Panjwani
  • Publication number: 20150192633
    Abstract: The embodiments of the present invention relate to semiconductor device manufacturing, and more particularly to structures and methods of directly testing semiconductor wafers having micro-solder connections. According to one embodiment of the present invention, a method of forming a pattern of micro-solder connections coupled with a through substrate via (TSV) that can be directly tested by electrical probing, without the use of a testing interposer, is disclosed. According to another embodiment, a method of testing the pattern of micro-solder connections is disclosed. According to another embodiment, a novel electrical probe tip structure, having contacts on the same pitch as the pattern of micro-solder connections is disclosed.
    Type: Application
    Filed: January 7, 2014
    Publication date: July 9, 2015
    Applicant: International Business Machines Corporation
    Inventors: Victor A. Garibay, Chetan Mehta, Doorlabh Panjwani, Tingdong Zhou