Patents by Inventor Dorav KUMAR
Dorav KUMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10459510Abstract: In certain aspects, an apparatus includes a first plurality of power switch devices. Each of the first plurality of power switch devices includes a delay line having a programmable time delay, and a power switch coupled between a supply rail and a circuit block, wherein the power switch has a control input coupled to the delay line. The apparatus also includes a switch manager configured to program the time delays of the delay lines in the first plurality of power switch devices based on a number of active circuit blocks in a system.Type: GrantFiled: January 17, 2019Date of Patent: October 29, 2019Assignee: QUALCOMM IncorporatedInventors: Raghavendra Srinivas, Uday Shankar Mudigonda, Giby Samson, Ramaprasath Vilangudipitchai, Dorav Kumar
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Patent number: 10103626Abstract: A power multiplexor includes: a first branch including a first transistor coupled in series with a second transistor between a first power supply and a power output; a second branch including a third transistor coupled in series with a fourth transistor between a second power supply and the power output; a controller configured to selectively assert and de-assert a control signal to the first branch and the second branch; a first voltage level shifter coupled between the second transistor and the controller; and a second voltage level shifter coupled between the third transistor and the controller.Type: GrantFiled: July 12, 2017Date of Patent: October 16, 2018Assignee: QUALCOMM IncorporatedInventors: Venkatasubramanian Narayanan, Dorav Kumar, Ramaprasath Vilangudipitchai, Venugopal Boynapalli
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Patent number: 10026735Abstract: A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.Type: GrantFiled: November 23, 2016Date of Patent: July 17, 2018Assignee: QUALCOMM IncorporatedInventors: Andi Zhao, Ramaprasath Vilangudipitchai, Dorav Kumar
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Publication number: 20180158506Abstract: The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.Type: ApplicationFiled: December 6, 2016Publication date: June 7, 2018Inventors: Dorav KUMAR, Venkat NARAYANAN, Bilal ZAFAR, Seid Hadi RASOULI, Venugopal BOYNAPALLI
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Patent number: 9990984Abstract: The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.Type: GrantFiled: December 6, 2016Date of Patent: June 5, 2018Assignee: QUALCOMM IncorporatedInventors: Dorav Kumar, Venkat Narayanan, Bilal Zafar, Seid Hadi Rasouli, Venugopal Boynapalli
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Publication number: 20180145071Abstract: A MOS IC includes pMOS transistors, each having a pMOS transistor drain, source, and gate. Each pMOS transistor gate extends in a first direction and is coupled to other pMOS transistor gates. Each pMOS transistor source/drain are coupled to a first voltage source. The MOS IC further includes a first metal interconnect extending over the pMOS transistors. The first metal interconnect has first and second ends. The first metal interconnect is coupled to each pMOS transistor gate and is coupled to a second voltage source less than the first voltage source. One of each pMOS transistor gate or the second voltage source is coupled to the first metal interconnect through at least one tap point located between the first and second ends. The pMOS transistors and the first metal interconnect function as a decoupling capacitor.Type: ApplicationFiled: November 23, 2016Publication date: May 24, 2018Inventors: Andi ZHAO, Ramaprasath VILANGUDIPITCHAI, Dorav KUMAR
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Patent number: 9859891Abstract: A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.Type: GrantFiled: June 24, 2016Date of Patent: January 2, 2018Assignee: QUALCOMM IncorporatedInventors: Dorav Kumar, Venkatasubramanian Narayanan, Bala Krishna Thalla, Seid Hadi Rasouli, Radhika Vinayak Guttal, Sivakumar Paturi
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Publication number: 20170373689Abstract: A MOS device may include a first logic component with a first input located on a second track and a first output located on the third track. The MOS device may include a second logic component with a second input located on the fourth track and a second output located on a fifth track. For example, the MOS device includes a first interconnect on a Mx layer that is coupled to the first input on the second track. In another example, the MOS device includes a second interconnect on the Mx layer that is coupled to the first output on the third track. The MOS device includes a third interconnect on a My layer that is coupled to the second input on the fourth track. Still further, the MOS device includes a fourth interconnect on the My layer that is coupled to the second output on the fifth track.Type: ApplicationFiled: June 24, 2016Publication date: December 28, 2017Inventors: Dorav KUMAR, Venkatasubramanian NARAYANAN, Bala Krishna THALLA, Seid Hadi RASOULI, Radhika Vinayak GUTTAL, Sivakumar PATURI
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Patent number: 9852859Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.Type: GrantFiled: December 28, 2015Date of Patent: December 26, 2017Assignee: QUALCOMM IncorporatedInventors: Lipeng Cao, Dorav Kumar, Bilal Zafar, Ramaprasath Vilangudipitchai, Venkatasubramanian Narayanan, Xi Luo
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Publication number: 20170186576Abstract: An integrated circuit (IC) is disclosed herein for adjustable power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC further includes multiple power-multiplexer (power-mux) tiles and adjustment circuitry. The multiple power-mux tiles are coupled in series in a chained arrangement and implemented to jointly perform a power-multiplexing operation. Each power-mux tile is implemented to switch between coupling the load power rail to the first power rail and coupling the load power rail to the second power rail. The adjustment circuitry is implemented to adjust at least one order in which the multiple power-mux tiles perform at least a portion of the power-multiplexing operation.Type: ApplicationFiled: December 28, 2015Publication date: June 29, 2017Inventors: Lipeng Cao, Dorav Kumar, Bilal Zafar, Ramaprasath Vilangudipitchai, Venkatasubramanian Narayanan, Xi Luo
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Patent number: 9685940Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.Type: GrantFiled: August 4, 2015Date of Patent: June 20, 2017Assignee: QUALCOMM IncorporatedInventors: Ramaprasath Vilangudipitchai, Dorav Kumar, Steven James Dillen, Ohsang Kwon, Javid Jaffari
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Patent number: 9654101Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.Type: GrantFiled: July 30, 2015Date of Patent: May 16, 2017Assignee: QUALCOMM IncorporatedInventors: Lipeng Cao, Divjyot Bhan, Ramaprasath Vilangudipitchai, Dorav Kumar
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Patent number: 9634026Abstract: A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.Type: GrantFiled: July 13, 2016Date of Patent: April 25, 2017Assignee: QUALCOMM INCORPORATEDInventors: Satyanarayana Sahu, Xiangdong Chen, Ramaprasath Vilangudipitchai, Dorav Kumar
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Publication number: 20170033796Abstract: An integrated circuit (IC) is disclosed herein for power management through power rail multiplexing. In an example aspect, an IC includes a first power rail, a second power rail, and a load power rail. The IC also includes a first set of transistors including first transistors that are coupled to the first power rail and a second set of transistors including second transistors that are coupled to the second power rail. The IC further includes power-multiplexer circuitry that is configured to switch access to power for the load power rail from the first power rail to the second power rail by sequentially turning off the first transistors of the first set of transistors and then sequentially turning on the second transistors of the second set of transistors.Type: ApplicationFiled: July 30, 2015Publication date: February 2, 2017Inventors: Lipeng Cao, Divjyot Bhan, Ramaprasath Vilangudipitchai, Dorav Kumar
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Patent number: 9483600Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.Type: GrantFiled: March 11, 2015Date of Patent: November 1, 2016Assignee: QUALCOMM INCORPORATEDInventors: Mamta Bansal, Uday Doddannagari, Paras Gupta, Ramaprasath Vilangudipitchai, Parissa Najdesamii, Dorav Kumar, Nitin Partani
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Publication number: 20160248414Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.Type: ApplicationFiled: August 4, 2015Publication date: August 25, 2016Inventors: Ramaprasath Vilangudipitchai, Dorav Kumar, Steven James Dillen, Ohsang Kwon, Javid Jaffari
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Publication number: 20150262936Abstract: A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.Type: ApplicationFiled: March 11, 2015Publication date: September 17, 2015Inventors: Mamta BANSAL, Uday DODDANNAGARI, Paras GUPTA, Ramaprasath VILANGUDIPITCHAI, Parissa NAJDESAMII, Dorav KUMAR, Nitin PARTANI