Patents by Inventor Doron GANON
Doron GANON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152362Abstract: Rather than waiting on a squelch to detect the difference in the state from steady to floating, this disclosure suggests using the time from when a reference clock is turned on to begin the process to exit the hibernation state. The reference clock is turned off while a data storage device is in the hibernation state to save power. Once the host is ready for the device to exit the hibernation state, the reference clock is turned on. The reference clock is monitored for the change. Once the reference clock is on, the data storage device returns to a steady state. In the ready state, the data storage device has a shortened ready time. Once the ready time is complete, the data storage device may now exit the hibernation state without waiting on squelch detection or a hibernation exit request from the host.Type: ApplicationFiled: July 17, 2023Publication date: May 9, 2024Applicant: Western Digital Technologies, Inc.Inventors: Doron GANON, Eitan LERNER
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Patent number: 11907577Abstract: A plurality of commands is received from at least one application. A command of the plurality of commands is to be performed by a Data Storage Device (DSD) after one or more conditions have been satisfied by the DSD. The plurality of commands is enqueued and the command is enqueued with the one or more conditions for performing the command. It is determined whether the one or more conditions have been satisfied by the DSD, and in response to determining that the one or more conditions have been satisfied by the DSD, the command is sent to the DSD for performance of the command.Type: GrantFiled: December 6, 2021Date of Patent: February 20, 2024Assignee: Western Digital Technologies, Inc.Inventors: Tomer Spector, Doron Ganon, Eran Arad
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Patent number: 11893281Abstract: A storage device includes a non-volatile memory (NVM) and a storage device controller. The storage device controller includes a NVM interface coupled to the NVM and one or more task queues. The storage device controller is operable to pick a task from one or more queues of the storage device. The task is parsed based upon presence of an extra header segment with an execution condition. The task without the extra header segment is sent to execution. Whether the execution condition of the extra header segment of the task is met is determined. The task with the execution condition met is sent to execution. The task with the execution condition unmet is postponed.Type: GrantFiled: February 28, 2022Date of Patent: February 6, 2024Assignee: Western Digital Technologies, Inc.Inventors: Tomer Spector, Doron Ganon, Eran Arad
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Publication number: 20230305058Abstract: The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYs (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.Type: ApplicationFiled: May 16, 2023Publication date: September 28, 2023Applicant: Western Digital Technologies, Inc.Inventors: Doron GANON, Eitan LERNER
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Patent number: 11687483Abstract: Disclosed herein are devices and systems that embed a physical layer (e.g., an M-PHY) on a configurable integrated circuit (e.g., an FPGA) and include glue hardware that provides AC coupling between a high-speed serial communication device (e.g., a MIPI device) and the configurable integrated circuit. The glue hardware provides AC coupling using only resistors, capacitors, and inductors. The configurable integrated circuit includes a logic block that manages the operation to provide the desired PHY connectivity. Because the disclosed devices and systems use AC coupling, the signaling drive and receive paths are controlled based on the received signal frequency and not based on the mode (e.g., LS mode or HS mode). Specifically, the line state of the MIPI device is inferred from observation of signal transitions as opposed to direct detection of DC signal levels.Type: GrantFiled: December 5, 2021Date of Patent: June 27, 2023Assignee: Western Digital Technologies, Inc.Inventors: Doron Ganon, Ofer Shahar, Or Faerman
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Patent number: 11675008Abstract: The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYs (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.Type: GrantFiled: February 28, 2020Date of Patent: June 13, 2023Assignee: Western Digital Technologies, Inc.Inventors: Doron Ganon, Eitan Lerner
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Publication number: 20230176781Abstract: A plurality of commands is received from at least one application. A command of the plurality of commands is to be performed by a Data Storage Device (DSD) after one or more conditions have been satisfied by the DSD. The plurality of commands is enqueued and the command is enqueued with the one or more conditions for performing the command. It is determined whether the one or more conditions have been satisfied by the DSD, and in response to determining that the one or more conditions have been satisfied by the DSD, the command is sent to the DSD for performance of the command.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Inventors: Tomer Spector, Doron Ganon, Eran Arad
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Publication number: 20230176996Abstract: Disclosed herein are devices and systems that embed a physical layer (e.g., an M-PHY) on a configurable integrated circuit (e.g., an FPGA) and include glue hardware that provides AC coupling between a high-speed serial communication device (e.g., a MIPI device) and the configurable integrated circuit. The glue hardware provides AC coupling using only resistors, capacitors, and inductors. The configurable integrated circuit includes a logic block that manages the operation to provide the desired PHY connectivity. Because the disclosed devices and systems use AC coupling, the signaling drive and receive paths are controlled based on the received signal frequency and not based on the mode (e.g., LS mode or HS mode). Specifically, the line state of the MIPI device is inferred from observation of signal transitions as opposed to direct detection of DC signal levels.Type: ApplicationFiled: December 5, 2021Publication date: June 8, 2023Applicant: Western Digital Technologies, Inc.Inventors: Doron GANON, Ofer SHAHAR, Or FAERMAN
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Publication number: 20220179587Abstract: A storage device includes a non-volatile memory (NVM) and a storage device controller. The storage device controller includes a NVM interface coupled to the NVM and one or more task queues. The storage device controller is operable to pick a task from one or more queues of the storage device. The task is parsed based upon presence of an extra header segment with an execution condition. The task without the extra header segment is sent to execution. Whether the execution condition of the extra header segment of the task is met is determined. The task with the execution condition met is sent to execution. The task with the execution condition unmet is postponed.Type: ApplicationFiled: February 28, 2022Publication date: June 9, 2022Applicant: Western Digital Technologies, Inc.Inventors: Tomer SPECTOR, Doron GANON, Eran ARAD
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Patent number: 11294832Abstract: A method for executing device management commands includes providing a device management command queue indication. The method also includes receiving, from a host in response to providing the device management command queue indication, device management commands and a respective command type for each device management command. The method also includes determining a command execution order for the device management commands based on the command types corresponding to respective device management commands and queueing, in a device management command queue, the device management commands based on the command execution order. The method also includes executing the device management commands according to the device management command queue. The method also includes communicating, to the host, a command execution indication responsive to executing the device management commands.Type: GrantFiled: March 20, 2020Date of Patent: April 5, 2022Assignee: Western Digital Technologies, Inc.Inventors: Doron Ganon, Edris Abzakh, Tomer Spector
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Patent number: 11275527Abstract: A storage device includes a non-volatile memory (NVM) and a storage device controller. The storage device controller includes a NVM interface coupled to the NVM and one or more task queues. The storage device controller is operable to pick a task from one or more queues of the storage device. The task is parsed based upon presence of an extra header segment with an execution condition. The task without the extra header segment is sent to execution. Whether the execution condition of the extra header segment of the task is met is determined. The task with the execution condition met is sent to execution. The task with the execution condition unmet is postponed.Type: GrantFiled: June 11, 2019Date of Patent: March 15, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Tomer Spector, Doron Ganon, Eran Arad
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Publication number: 20210294758Abstract: A method for executing device management commands includes providing a device management command queue indication. The method also includes receiving, from a host in response to providing the device management command queue indication, device management commands and a respective command type for each device management command. The method also includes determining a command execution order for the device management commands based on the command types corresponding to respective device management commands and queueing, in a device management command queue, the device management commands based on the command execution order. The method also includes executing the device management commands according to the device management command queue. The method also includes communicating, to the host, a command execution indication responsive to executing the device management commands.Type: ApplicationFiled: March 20, 2020Publication date: September 23, 2021Applicant: Western Digital Technologies, Inc.Inventors: Doron Ganon, Edris Abzakh, Tomer Spector
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Publication number: 20210270896Abstract: The present disclosure generally relates to an embedded physical layer (EPHY) for a field programmable gate array (FPGA). The EPHY for the FPGA is for a testing device that can receive and transmit in both the high speed PHYs, as well as low speed PHYs, such as MIPI PHYs (MPHYs), to meet universal flash storage (UFS) specifications. The testing device with the EPHY for the FPGA provides flexibility to support any specification updates without the need of application specific (ASIC) production cycles.Type: ApplicationFiled: February 28, 2020Publication date: September 2, 2021Inventors: Doron GANON, Eitan LERNER