Abstract: A self-powered electronic shelf label (ESL), comprising: a processing circuitry; a display communicatively coupled to the processing circuitry; a communication circuit communicatively coupled to the processing circuitry, wherein the communication circuit is configured to receive and transmit data from a control device; and a power manager connected to the processing circuitry, the display, an energy storage, and a plurality of photovoltaic (PV) cells, the power manager including a maximum power point tracker (MPPT) circuit, wherein the MPPT circuit is configured to continuously determine a maximum power point of the PV cells, wherein the power manager is configured to connect, based on the determined maximum power point, at least a portion of the plurality of PV cells to a load such that the plurality of PV cells produce a voltage equal to the continuously determined maximum power point.

Abstract: A microchip structure and a method for manufacturing thereof are provided. The microchip structure comprises a target integrated circuit (TIC) comprising a first surface and a first power contact at a first location on the first surface of the TIC, the TIC further comprising a second power contact at a second location on the first surface of the TIC; a plurality of photovoltaic (PV) diodes deposited on a first surface of a transparent substrate, each of the PV diodes having an anode coupled to an anode contact and a cathode coupled to a cathode contact, the transparent substrate is transparent to an electromagnetic frequency to which the PV diodes are sensitive; the cathode contact of a first PV diode of the PV diodes is bonded to the first power contact and the anode contact of a second PV diode of the PV diodes is bonded to the second power contact.

Abstract: A self-powered electronic shelf label (ESL), comprising: a processing circuitry; a display communicatively coupled to the processing circuitry; a communication circuit communicatively coupled to the processing circuitry, wherein the communication circuit is configured to receive and transmit data from a control device; and a power manager connected to the processing circuitry, the display, an energy storage, and a plurality of photovoltaic (PV) cells, the power manager including a maximum power point tracker (MPPT) circuit, wherein the MPPT circuit is configured to continuously determine a maximum power point of the PV cells, wherein the power manager is configured to connect, based on the determined maximum power point, at least a portion of the plurality of PV cells to a load such that the plurality of PV cells produce a voltage equal to the continuously determined maximum power point.

Abstract: A microchip structure and a method for manufacturing thereof are provided. The microchip structure comprises a target integrated circuit (TIC) comprising a first surface and a first power contact at a first location on the first surface of the TIC, the TIC further comprising a second power contact at a second location on the first surface of the TIC; a plurality of photovoltaic (PV) diodes deposited on a first surface of a transparent substrate, each of the PV diodes having an anode coupled to an anode contact and a cathode coupled to a cathode contact, the transparent substrate is transparent to an electromagnetic frequency to which the PV diodes are sensitive; the cathode contact of a first PV diode of the PV diodes is bonded to the first power contact and the anode contact of a second PV diode of the PV diodes is bonded to the second power contact.

Abstract: An integrated circuit (IC) comprises a plurality of photovoltaic (PV) cells formed over a passivation layer of a target integrated circuit (TIC), wherein at least one PV cell of the plurality of PV cells is usable as a light sensing device; an interface to an energy storage unit; the TIC comprising at least: a control unit; and a switching circuit, the switching circuit coupled to the plurality of PV cells, the energy storage, and the control unit; wherein the control unit is configured to control at least the switching circuit to configure a connection scheme, wherein the connection scheme devises at least one first PV cell of the plurality of PV cells to connect to the energy storage and at least one second PV cell to connect to the control unit for light detection.

Abstract: An integrated circuit (IC) comprises a plurality of photovoltaic (PV) cells formed over a passivation layer of a target integrated circuit (TIC), wherein at least one PV cell of the plurality of PV cells is usable as a light sensing device; an interface to an energy storage unit; the TIC comprising at least: a control unit; and a switching circuit, the switching circuit coupled to the plurality of PV cells, the energy storage, and the control unit; wherein the control unit is configured to control at least the switching circuit to configure a connection scheme, wherein the connection scheme devises at least one first PV cell of the plurality of PV cells to connect to the energy storage and at least one second PV cell to connect to the control unit for light detection.

Abstract: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFill™ technology or by mechanical pressing.

Abstract: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFill™ technology or by mechanical pressing.

Abstract: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFill™ technology or by mechanical pressing.

Abstract: An X-ray image sensor having scintillating material embedded into wave-guide structures fabricated in a CMOS image sensor (CIS). After the CIS has been fabricated, openings (deep pores) are formed in the back side of the CIS wafer. These openings terminate at a distance of about 1 to 5 microns below the upper silicon surface of the wafer. The depth of these openings can be controlled by stopping on a buried insulating layer, or by stopping on an epitaxial silicon layer having a distinctive doping concentration. The openings are aligned with corresponding photodiodes of the CIS. The openings may have a shape that narrows as approaching the photodiodes. A thin layer of a reflective material may be formed on the sidewalls of the openings, thereby improving the efficiency of the resulting waveguide structures. Scintillating material (e.g., CsI(Tl)) is introduced into the openings using a ForceFill™ technology or by mechanical pressing.