Abstract: A time delay circuit for providing a delayed replica of a digital input signal including first and second counters for providing first and second count outputs offset relative to each other by a predetermined value indicative of a predetermined delay, and further including a first-in first-out (FIFO) memory for controllably storing selected values of the digital input signal together with corresponding first count output values. First comparison circuitry compares each digital input with the immediately prior digital input, and controls the FIFO memory to store (a) each digital input which is different from the immediately prior digital input, and (b) the first counter output value associated therewith.