Patents by Inventor Douglas B. Hershberger
Douglas B. Hershberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9257324Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.Type: GrantFiled: March 31, 2014Date of Patent: February 9, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Robert M. Rassel, Mark E. Stidham
-
Publication number: 20140213036Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.Type: ApplicationFiled: March 31, 2014Publication date: July 31, 2014Applicant: International Business Machines CorporationInventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Robert M. Rassel, Mark E. Stidham
-
Patent number: 8735986Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.Type: GrantFiled: December 6, 2011Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Robert M. Rassel, Mark E. Stidham
-
Patent number: 8466501Abstract: An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).Type: GrantFiled: May 21, 2010Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Douglas B. Hershberger, Richard A. Phelps, Robert M. Rassel, Stephen A. St. Onge, Michael J. Zierak
-
Publication number: 20130140668Abstract: A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan B. Botula, Renata Camillo-Castillo, James S. Dunn, Jeffrey P. Gambino, Douglas B. Hershberger, Alvin J. Joseph, Mark E. Stidham, Robert M. Rassel
-
Publication number: 20110284930Abstract: An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).Type: ApplicationFiled: May 21, 2010Publication date: November 24, 2011Applicant: International Business Machines CorporationInventors: Douglas B. Hershberger, Richard A. Phelps, Robert M. Rassel, Stephen A. St. Onge, Michael J. Zierak
-
Patent number: 7807562Abstract: A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.Type: GrantFiled: October 22, 2008Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: Douglas B. Hershberger, Steven H. Voldman, Michael J. Zierak
-
Patent number: 7714412Abstract: The present invention provides a varactor that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate of a first conductivity type and optionally a subcollector or isolation well (i.e., doped region) of a second conductivity type located below an upper region of the substrate, the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions are formed in the upper region of the substrate and then a well region is formed in the upper region of the substrate. In some cases, the doped region is formed at this point of the inventive process. The well region includes outer well regions of the second conductivity type and an inner well region of the first conductivity type.Type: GrantFiled: August 27, 2004Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Douglas B. Hershberger, Robert M. Rassel
-
Publication number: 20090035933Abstract: A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.Type: ApplicationFiled: October 22, 2008Publication date: February 5, 2009Applicant: INTERNATIONAL BUSNESS MACHINES CORPORATIONInventors: Douglas B. Hershberger, Steven H. Voldman, Michael J. Zierak
-
Patent number: 7473643Abstract: A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.Type: GrantFiled: August 1, 2006Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Douglas B. Hershberger, Steven H. Voldman, Michael J. Zierak
-
Patent number: 7393701Abstract: Methods of adjusting a resistance of a buried resistor in a semiconductor are disclosed. In one aspect, the method includes using a silicidation blocking mask to define the buried resistor in the semiconductor; adjusting a size of the silicidation blocking mask to adjust a resistance of the buried resistor based on test data from a previous processing lot including a substantially similar buried resistor; and forming silicide on an area not covered by the silicidation blocking mask. The adjustment may be made by balancing the amount of the resistor that is covered with silicide versus un-silicided semiconductor to achieve the desired total resistance. The adjustment may be made according to an algorithm.Type: GrantFiled: December 5, 2006Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: Douglas B. Hershberger, Alain Loiseau, Kirk D. Peterson, Robert M. Rassel
-
Publication number: 20080131980Abstract: Methods of adjusting a resistance of a buried resistor in a semiconductor are disclosed. In one aspect, the method includes using a silicidation blocking mask to define the buried resistor in the semiconductor; adjusting a size of the silicidation blocking mask to adjust a resistance of the buried resistor based on test data from a previous processing lot including a substantially similar buried resistor; and forming silicide on an area not covered by the silicidation blocking mask. The adjustment may be made by balancing the amount of the resistor that is covered with silicide versus un-silicided semiconductor to achieve the desired total resistance. The adjustment may be made according to an algorithm.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Applicant: International Business Machines CorporationInventors: Douglas B. Hershberger, Alain Loiseau, Kirk D. Peterson, Robert M. Rassel
-
Patent number: 7109584Abstract: A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.Type: GrantFiled: November 23, 2004Date of Patent: September 19, 2006Assignee: International Business Machines CorporationInventors: Douglas B. Hershberger, Steven H. Voldman, Michael J. Zierak
-
Patent number: 6396107Abstract: A silicon-germanium ESD element comprises a substrate of a first dopant type coupled to a first voltage terminal and a first diode-configured element. The first diode-configured element has a collector region of a second dopant type in the substrate, a SiGe base layer of the first dopant type on the collector region, with the SiGe base layer including a base contact region, and an emitter of the second dopant type on the SiGe base layer. Preferably, the SiGe base layer ion the collector region is an epitaxial SiGe layer and the second dopant type of the emitter is diffused in to the SiGe base layer. The ESD element of the present invention may further include a second diode-configured element of the same structure as the first diode-configured element, with an isolation region in the substrate separating the first and second diode-configured elements. The first and second diode-configured elements form a diode network.Type: GrantFiled: November 20, 2000Date of Patent: May 28, 2002Assignee: International Business Machines CorporationInventors: Ciaran J. Brennan, Douglas B. Hershberger, Mankoo Lee, Nicholas T. Schmidt, Steven H. Voldman