Abstract: An apparatus and method is provided for correcting data words resulting from a package fail within a memory array in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error correcting code bits and n-r data bits. The invention is capable of correcting one package which has suffered at least one hard failure. The invention correcting exploits single error correcting (SEC)-and double error detecting (DED) codes, requiring no additional check bits, which give a syndrome when the data word has suffered an error coming from at least one error in a package.

Abstract: A single width bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear centimeter, an important consideration in semiconductor manufacturing wherein space on the chips and the wafer is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.

Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Abstract: A method and apparatus is provided for producing single width barcodes in a continuous, serpentine pattern. This pattern provides continuity of operation for laser marking instruments and thereby results in the formation of more uniform and higher quality barcode indicia. The use of a continuous serpentine pattern also increases the speed at which the code may be written onto a substrate. This marking method is particularly appropriate for use in marking a wide variety of materials including semiconductors, metals, plastics and ceramics.

Abstract: A single width bar code is appended with an end mark which includes a blank interval and a bar. The resulting bar code is bidirectional and inherently self clocking so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described are robust, reliable, and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear measurements, an important consideration in semiconductor manufacturing wherein space on chips and wafers is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.

Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Abstract: An error correction coding system employs a single check symbol from an arbitrary sequence of information symbols to provide single error correction at the symbol level. The sequence of information symbols may in fact also be arbitrarily long. The coding system of the present invention provides both a method and apparatus for encoding the check symbol and a method and apparatus for error correction based upon the single coded symbol character. The system is particularly applicable for use in conjunction with bar code recognition systems but is in fact applicable to a broad range of coding systems, including optical character recognition and ordinary alphanumeric codes. The system is also extendable to any system employing an odd number of code symbols that may be present in a single character position.

Abstract: In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

Abstract: Swapping of bits between different words of a memory is accomplished by reference to data on bad bits in the memory. This data controls address inputs to each bit in a memory word so that any word with multiple uncorrectable data is changed to a correctable data word by placing one or more of the bad bits in the word into another word of the memory. The swapping is done by an exclusionary process which deselects certain combinations of addresses thereby limiting the selection process to other combinations. The process can involve categorizing of failures in accordance with type and performing algorithm operations which identify combinations of bit addresses that would result in combining the failures so that there are more errors in any memory word than would be correctable by the error correction code monitoring the memory.

Abstract: A single error correcting double error detecting (SEC/DED) error correcting code for a memory is used to correct one fixed error and one transitory error in a data word stored in the memory. The erroneous data word and syndrome generated therefrom by the error correcting code circuitry are saved while the memory location of the flawed word is checked to determine the location of the one fixed error using a ancillatory error correction technique. A syndrome is then generated for the word assuming only a single fixed error in the location determined using the ancillatory technique. Thereafter, the generated and saved syndromes are exclusive OR'd together to obtain another syndrome locating the position of the transitory error. With both errors located, the word is corrected by inverting the erroneous data bits.