Abstract: A system for using free-space optics to interconnect a plurality of computing nodes can include a plurality of optical transceivers that facilitate free-space optical communications among the plurality of computing nodes. The system may ensure a line of sight between the plurality of computing nodes and the optical transceivers to facilitate the free-space optical communications. The line of sight may be preserved by the position or placement of the computing nodes in the system. The position or placement of the computing nodes may be achieved by using different shaped enclosures for holding the computing nodes.

Abstract: A quantum computing device comprises a surface code lattice that includes l logical qubits, where l is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the l logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Abstract: A quantum computing device comprises a surface code lattice that includes l logical qubits, where l is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the l logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Abstract: A quantum computing device comprises a surface code lattice that includes/logical qubits, where/is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the/logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Abstract: A system for using free-space optics to interconnect a plurality of computing nodes can include a plurality of optical transceivers that facilitate free-space optical communications among the plurality of computing nodes. The system may ensure a line of sight between the plurality of computing nodes and the optical transceivers to facilitate the free-space optical communications. The line of sight may be preserved by the position or placement of the computing nodes in the system. The position or placement of the computing nodes may be achieved by using different shaped enclosures for holding the computing nodes.

Abstract: A system includes a synthesizer unit having a fluid input to receive fluids and a communication input to receive commands to synthesize data-encoded DNA sequences and cleave the DNA. A first flexible chemistry reaction chamber module may be fluidically coupled to the synthesizer unit to receive the data-encoded DNA sequences and amplify the sequences. A deposition unit may be fluidically coupled to the first flexible chemistry reaction chamber module to receive the amplified DNA sequences and encapsulate the amplified DNA sequences into one or more wells in a storage plate for storage and retrieval to and from a plate storage unit. Retrieved DNA may be processed and read by further units.

Abstract: A system for using free-space optics to interconnect a plurality of computing nodes can include a plurality of optical transceivers that facilitate free-space optical communications among the plurality of computing nodes. The system may ensure a line of sight between the plurality of computing nodes and the optical transceivers to facilitate the free-space optical communications. The line of sight may be preserved by the position or placement of the computing nodes in the system. The position or placement of the computing nodes may be achieved by using different shaped enclosures for holding the computing nodes.

Abstract: A system includes a synthesizer unit having a fluid input to receive fluids and a communication input to receive commands to synthesize data-encoded DNA sequences and cleave the DNA. A first flexible chemistry reaction chamber module may be fluidically coupled to the synthesizer unit to receive the data-encoded DNA sequences and amplify the sequences. A deposition unit may be fluidically coupled to the first flexible chemistry reaction chamber module to receive the amplified DNA sequences and encapsulate the amplified DNA sequences into one or more wells in a storage plate for storage and retrieval to and from a plate storage unit. Retrieved DNA may be processed and read by further units.

Abstract: A quantum computing device comprises at least one quantum register including a plurality of logical qubits. A compression engine is coupled to each logical qubit of the plurality of logical qubits. Each compression engine is configured to compress syndrome data. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Abstract: A quantum computing device comprises at least one quantum register including l logical qubits, where l is a positive integer. The quantum computing device further includes a set of d decoder blocks coupled to the at least one quantum register, where d<2*l. In this way, the decoder blocks may share decoding requests generated by the logical qubits.

Abstract: A quantum computing device comprises at least one quantum register including a plurality of qubits, and a hardware decoder. The hardware decoder is configured to: receive syndrome data from one or more of the plurality of qubits; and decode the received syndrome data by implementing a Union-Find decoding algorithm via a hardware microarchitecture including two or more pipeline stages.

Abstract: A quantum computing device comprises at least one quantum register including a plurality of logical qubits. A compression engine is coupled to each logical qubit of the plurality of logical qubits. Each compression engine is configured to compress syndrome data. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Abstract: A system includes a synthesizer unit having a fluid input to receive fluids and a communication input to receive commands to synthesize data-encoded DNA sequences and cleave the DNA. A first flexible chemistry reaction chamber module may be fluidically coupled to the synthesizer unit to receive the data-encoded DNA sequences and amplify the sequences. A deposition unit may be fluidically coupled to the first flexible chemistry reaction chamber module to receive the amplified DNA sequences and encapsulate the amplified DNA sequences into one or more wells in a storage plate for storage and retrieval to and from a plate storage unit. Retrieved DNA may be processed and read by further units.

Abstract: A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract: One example embodiment includes a circuit system. The system includes a wave-pipelined combinational logic circuit comprising at least one logic gate between an input node and at least one output node and configured to perform logic operations on a data sequence received at the input node. The system also includes a scan path connected to the input node and comprising at least one delay element configured to propagate the data sequence from the input to a scan path output to capture values of the data sequence provided to the wave-pipelined combinational logic circuit as a serial data stream. The system also includes a scan point device configured to deliver one of input data and scan data as the data sequence to the wave-pipelined combinational logic circuit and to the scan path via the input node in a respective one of a normal operating mode and a scan mode.

Abstract: Techniques are disclosed to control power and processing among a plurality of asymmetric cores.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract: A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.

Abstract: A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.