Abstract: A method for maintaining memory coherency in a data processing system is disclosed. The data processing system includes a memory system having a dual bus memory controller, which is coupled to a first bus through a first bus master and a second bus coupled to a second bus master. The method maintains memory coherency by snooping across either the first or second bus for attributes on an address/data multiplex bus in the data processing unit. To determine when a snoop operation is required, the system begins by requesting access to either of the two buses through the dual bus memory controller. Once the control of the bus has been granted upon request data is transferred using the master bus controller. It is upon the receipt of an invalid data signal while transferring data across the bus that the snoop activity begins. The snoop is injected only after an invalid data signal is received and a last snoop injection can occur only before a last read data is read.

Abstract: A protocol and system for providing a next read address during an address phase of a write transaction in a data cache unit in a processing unit is disclosed. The processing unit includes the data cache unit and an instruction cache unit both coupled to an address bus and a data bus, respectively. The two buses are further connected to a system memory controller separate from the microprocessor. The protocol and system provide for next read address and a next transaction during the address phase in a current write transaction. The protocol loads a pre-fetched address within a current data transaction and then generates a next line fill address using the pre-fetched address which is concatenated to the current data transaction. The pre-fetched address is used to generate a next line fill address.