Abstract: Described herein are compounds that inhibit ALK2 and its mutants, pharmaceutical compositions including such compounds, and methods of using such compounds and compositions.

Abstract: A method and system for disabling functions of a movement detection enabled device is provided. The method includes monitoring a movement detection signal of the movement detection enabled device in a vehicle and determining that the vehicle is currently in motion. An electronic tag in the vehicle is detected and instructions associated with the movement detection enabled device are retrieved. It is determined that the movement detection enabled device is located within a specified proximity to a driver location of the vehicle and that a user of the device is a driver of the vehicle. In response, specified functions of the movement detection enabled device are disabled.

Abstract: A method and system for disabling functions of a movement detection enabled device is provided. The method includes monitoring a movement detection signal of the movement detection enabled device in a vehicle and determining that the vehicle is currently in motion. An electronic tag in the vehicle is detected and instructions associated with the movement detection enabled device are retrieved. It is determined that the movement detection enabled device is located within a specified proximity to a driver location of the vehicle and that a user of the device is a driver of the vehicle. In response, specified functions of the movement detection enabled device are disabled.

Abstract: A method and system for disabling functions of a movement detection enabled device is provided. The method includes monitoring a movement detection signal of the movement detection enabled device in a vehicle and determining that the vehicle is currently in motion. An electronic tag in the vehicle is detected and instructions associated with the movement detection enabled device are retrieved. It is determined that the movement detection enabled device is located within a specified proximity to a driver location of the vehicle and that a user of the device is a driver of the vehicle. In response, specified functions of the movement detection enabled device are disabled.

Abstract: A method and system for disabling functions of a movement detection enabled device is provided. The method includes monitoring a movement detection signal of the movement detection enabled device in a vehicle and determining that the vehicle is currently in motion. An electronic tag in the vehicle is detected and instructions associated with the movement detection enabled device are retrieved. It is determined that the movement detection enabled device is located within a specified proximity to a driver location of the vehicle and that a user of the device is a driver of the vehicle. In response, specified functions of the movement detection enabled device are disabled.

Abstract: A method and system for disabling functions of a movement detection enabled device is provided. The method includes monitoring a movement detection signal of the movement detection enabled device in a vehicle and determining that the vehicle is currently in motion. An electronic tag in the vehicle is detected and instructions associated with the movement detection enabled device are retrieved. It is determined that the movement detection enabled device is located within a specified proximity to a driver location of the vehicle and that a user of the device is a driver of the vehicle. In response, specified functions of the movement detection enabled device are disabled.

Abstract: A method and system for disabling functions of a movement detection enabled device is provided. The method includes monitoring a movement detection signal of the movement detection enabled device in a vehicle and determining that the vehicle is currently in motion. An electronic tag in the vehicle is detected and instructions associated with the movement detection enabled device are retrieved. It is determined that the movement detection enabled device is located within a specified proximity to a driver location of the vehicle and that a user of the device is a driver of the vehicle. In response, specified functions of the movement detection enabled device are disabled.

Abstract: A method and system for disabling functions of a movement detection enabled device is provided. The method includes monitoring a movement detection signal of the movement detection enabled device in a vehicle and determining that the vehicle is currently in motion. An electronic tag in the vehicle is detected and instructions associated with the movement detection enabled device are retrieved. It is determined that the movement detection enabled device is located within a specified proximity to a driver location of the vehicle and that a user of the device is a driver of the vehicle. In response, specified functions of the movement detection enabled device are disabled.

Abstract: A method and system for disabling functions of a movement detection enabled device is provided. The method includes monitoring a movement detection signal of the movement detection enabled device in a vehicle and determining that the vehicle is currently in motion. An electronic tag in the vehicle is detected and instructions associated with the movement detection enabled device are retrieved. It is determined that the movement detection enabled device is located within a specified proximity to a driver location of the vehicle and that a user of the device is a driver of the vehicle. In response, specified functions of the movement detection enabled device are disabled.

Abstract: A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

Abstract: An interrupting node for providing interrupt requests to a pended bus. The interrupting node provides to the pended bus an interrupt request message including ID data for identifying the interrupting node as the source of an interrupt request. An interrupt servicing node provides interrupt acknowledge messages including destination data specifying a particular interrupting node at times when the interrupt servicing node is ready to service an interrupt request message. The interrupting node detects whether an interrupt acknowledge message on the bus includes destination data specifying that interrupting node, and provides an interrupt vector message to the bus in response.

Abstract: A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performance of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.

Abstract: A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performance of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.

Abstract: A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the data that has been requested. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

Abstract: Apparatus and method for servicing interrupt requests on a pended bus. An interrupt servicing node provides interrupt acknowledge messages including destination data specifying a particular interrupting node at times when the interrupt servicing node is ready to service an interrupt request message. The interrupt servicing node includes storage for specifying the identity of a particular interrupting node and for indicating that an interrupt request is pending from a particular interrupting node. An interrupting node provides to the pended bus an interrupt request message including ID data for identifying the interrupting node as the source of an interrupt request. The interrupting node detects whether an interrupt acknowledge message on the bus includes destination data specifying that interrupting node.

Abstract: A computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processes in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue.

Abstract: Interrupt servicing node for servicing interrupt requests on a pended bus. The interrupt servicing node provides interrupt acknowledge messages including destination data specifying a particular interrupting node at times when the interrupt servicing node is ready to service the interrupt request message. The interrupt servicing node includes storage elements for indicating whether an interrupt request is pending from a particular interrupting node. An interrupt request message on the bus includes ID data for identifying a particular interrupting node as the source of an interrupt request.

Abstract: A memory node in a computer system having multiple processors interconnected by a pended bus provides exclusive read-modify-write operations employing multiple lock bits. A processor generates an interlock read command which is transmitted as a transfer over the pended bus to the memory node. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the processor transfer. The processor transfer, including an interlock read command, is stored in a input queue in memory and processed in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue.

Abstract: A processor node providing exclusive read-modify-write operations in a computer system having multiple processors interconnected by a pended bus and employing multiple lock bits. The processor generates an interlock read command which is transmitted as a transfer over the pended bus to a memory or I/O mode. Acknowledge confirmations are transmitted by the memory back to the processor two bus cycles after each bus cycle of the command transfer. The command transfer, including an interlock read command, is stored in an input queue in memory and is processed in turn by the memory. A first interlock read command to a specified memory location causes a lock bit to be set for that location and a first type of response message including the contents of the specified location to be generated by the memory and stored in an output queue.

Abstract: A multiple node computer system includes processor nodes, memory nodes, and input/output nodes interconnected on a pended bus. The system includes a lockout indicator which is set upon receipt of a locked response message by a processor node from a memory node in response to an interlock read command. The processors include a lockout check circuit responsive to the condition of the lockout indicator and will restrict generation of additional interlock read commands according to a predetermined access gating criterion until the lockout indicator is reset. In this manner, processor nodes of the system are assured equitable access to a memory node.