Patents by Inventor Douglas Duane Coolbaugh
Douglas Duane Coolbaugh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8969200Abstract: An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.Type: GrantFiled: April 12, 2012Date of Patent: March 3, 2015Assignee: The Research Foundation of State University of New YorkInventors: Jeremiah Hebding, Megha Rao, Colin McDonough, Matthew Smalley, Douglas Duane Coolbaugh, Joseph Piccirillo, Jr., Stephen G. Bennett, Michael Liehr, Daniel Pascual
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Patent number: 8697542Abstract: A method is provided for bonding a die to a base technology wafer and includes: providing a device wafer having a front, back, at least one side, and at least one TSV, wherein the back contains a substrate material; providing a carrier wafer having a front, back, and at least one side; bonding the wafers using an adhesive; removing the substrate material and wet etching, from the device wafer's back side, to expose at least one metallization scheme feature; processing the device wafer's back side to create at least one backside redistribution layer; removing the device wafer from the carrier wafer; dicing the device wafer into individual die; providing a base technology wafer; coating the front of the base technology wafer with a sacrificial adhesive; placing the front of the individual die onto the front of the base technology wafer; and bonding the individual die to the base technology wafer.Type: GrantFiled: April 12, 2012Date of Patent: April 15, 2014Assignee: The Research Foundation of State University of New YorkInventors: Daniel Pascual, Jeremiah Hebding, Megha Rao, Colin McDonough, Douglas Duane Coolbaugh, Joseph Piccirillo, Jr., Michael Liehr
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Publication number: 20130270711Abstract: An apparatus and method are provided for integrating TSVs into devices prior to device contacts processing. The apparatus includes a semiconducting layer; one or more CMOS devices mounted on a top surface of the semiconducting layer; one or more TSVs integrated into the semiconducting layer of the device wafer; at least one metal layer applied over the TSVs; and one or more bond pads mounted onto a top layer of the at least one metal layer, wherein the at least one metal layer is arranged to enable placement of the one or more bond pads at a specified location for bonding to a second device wafer. The method includes obtaining a wafer of semiconducting material, performing front end of line processing on the wafer; providing one or more TSVs in the wafer; performing middle of line processing on the wafer; and performing back end of line processing on the wafer.Type: ApplicationFiled: April 12, 2012Publication date: October 17, 2013Applicant: The Research Foundation Of State University Of New YorkInventors: Jeremiah HEBDING, Megha RAO, Colin McDONOUGH, Matthew SMALLEY, Douglas Duane COOLBAUGH, Joseph PICCIRILLO, JR., Stephen G. BENNETT, Michael LIEHR, Daniel PASCUAL
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Publication number: 20130273691Abstract: A method is provided for bonding a die to a base technology wafer and includes: providing a device wafer having a front, back, at least one side, and at least one TSV, wherein the back contains a substrate material; providing a carrier wafer having a front, back, and at least one side; bonding the wafers using an adhesive; removing the substrate material and wet etching, from the device wafer's back side, to expose at least one metallization scheme feature; processing the device wafer's back side to create at least one backside redistribution layer; removing the device wafer from the carrier wafer; dicing the device wafer into individual die; providing a base technology wafer; coating the front of the base technology wafer with a sacrificial adhesive; placing the front of the individual die onto the front of the base technology wafer; and bonding the individual die to the base technology wafer.Type: ApplicationFiled: April 12, 2012Publication date: October 17, 2013Applicant: THE RESEARCH FOUNDATION OF STATE UNIVERSITY OF NEW YORKInventors: Daniel PASCUAL, Jeremiah HEBDING, Megha RAO, Colin McDONOUGH, Douglas Duane COOLBAUGH, Joseph PICCIRILLO, JR., Michael LIEHR
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Patent number: 8390038Abstract: A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, a dielectric block comprising one or more dielectric layers, a lower plate comprising one or more electrically conductive layer; and a spreader plate comprising one or more electrically conductive layers.Type: GrantFiled: June 5, 2008Date of Patent: March 5, 2013Assignee: International Business Machines CorporationInventors: Douglas Duane Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Robert Mark Rassel
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Patent number: 7915134Abstract: A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.Type: GrantFiled: January 8, 2008Date of Patent: March 29, 2011Assignee: International Business Machines CorporationInventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, Keith Edward Downes, Ebenezer E. Eshun, Zhong-Xiang He, Robert Mark Rassel, Anthony Kendall Stamper, Kunal Vaed
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Patent number: 7763954Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad.Type: GrantFiled: July 10, 2008Date of Patent: July 27, 2010Assignee: International Business Machines CorporationInventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, John Edward Florkey, Jeffrey Peter Gambino, Zhong-Xiang He, Anthony Kendall Stamper, Kunal Vaed
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Patent number: 7741698Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer.Type: GrantFiled: July 16, 2008Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, John Edward Florkey, Jeffrey Peter Gambino, Zhong-Xiang He, Anthony Kendall Stamper, Kunal Vaed
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Patent number: 7732294Abstract: A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.Type: GrantFiled: July 10, 2008Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, John Edward Florkey, Jeffrey Peter Gambino, Zhong-Xiang He, Anthony Kendall Stamper, Kunal Vaed
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Patent number: 7732295Abstract: A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An inductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.Type: GrantFiled: July 10, 2008Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, John Edward Florkey, Jeffrey Peter Gambino, Zhong-Xiang He, Anthony Kendall Stamper, Kunal Vaed
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Patent number: 7713829Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.Type: GrantFiled: November 22, 2006Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Jack Oon Chu, Douglas Duane Coolbaugh, James Stuart Dunn, David R. Greenberg, David L. Harame, Basanth Jagannathan, Robb Allen Johnson, Louis D. Lanzerotti, Kathryn Turner Schonenberg, Ryan Wayne Wuthrich
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Patent number: 7573117Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer.Type: GrantFiled: July 16, 2008Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, John Edward Florkey, Jeffrey Peter Gambino, Zhong-Xiang He, Anthony Kendall Stamper, Kunal Vaed
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Patent number: 7488643Abstract: A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, the upper plate having a top surface, a bottom surface and sidewalls; a spreader plate comprising one or more electrically conductive layers, the spreader plate having a top surface, a bottom surface and sidewalls; and a dielectric block comprising one or more dielectric layers the dielectric block having a top surface, a bottom surface and sidewalls, the top surface of the dielectric block in physical contact with the bottom surface of the upper plate, the bottom surface of the dielectric block over the top surface of the spreader plate, the sidewalls of the upper plate and the dielectric block essentially co-planer.Type: GrantFiled: June 21, 2006Date of Patent: February 10, 2009Assignee: International Business Machines CorporationInventors: Douglas Duane Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Robert Mark Rassel
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Publication number: 20090004809Abstract: A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.Type: ApplicationFiled: January 8, 2008Publication date: January 1, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, Keith Edward Downes, Ebenezer E. Eshun, Zhong-Xiang He, Robert Mark Rassel, Anthony Kendall Stamper, Kunal Vaed
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Publication number: 20080290458Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad.Type: ApplicationFiled: July 10, 2008Publication date: November 27, 2008Inventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, John Edward Florkey, Jeffrey Peter Gambino, Zhong-Xiang He, Anthony Kendall Stamper, Kunal Vaed
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Publication number: 20080293210Abstract: A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An iductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.Type: ApplicationFiled: July 10, 2008Publication date: November 27, 2008Inventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, John Edward Florkey, Jeffrey Peter Gambino, Zhong-Xiang He, Anthony Kendall Stamper, Kunal Vaed
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Publication number: 20080293233Abstract: A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.Type: ApplicationFiled: July 10, 2008Publication date: November 27, 2008Inventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, John Edward Florkey, Jeffrey Peter Gambino, Zhong-Xiang He, Anthony Kendall Stamper, Kunal Vaed
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Publication number: 20080277759Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer.Type: ApplicationFiled: July 16, 2008Publication date: November 13, 2008Inventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, John Edward Florkey, Jeffrey Peter Gambino, Zhong-Xiang He, Anthony Kendall Stamper, Kunal Vaed
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Publication number: 20080272458Abstract: A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer.Type: ApplicationFiled: July 16, 2008Publication date: November 6, 2008Inventors: Anil Kumar Chinthakindi, Douglas Duane Coolbaugh, John Edward Florkey, Jeffrey Peter Gambino, Zhong-Xiang He, Anthony Kendall Stamper, Kunal Vaed
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Publication number: 20080232025Abstract: A MIM capacitor device and method of making the device. The device includes an upper plate comprising one or more electrically conductive layers, a dielectric block comprising one or more dielectric layers, a lower plate comprising one or more electrically conductive layer; and a spreader plate comprising one or more electrically conductive layers.Type: ApplicationFiled: June 5, 2008Publication date: September 25, 2008Inventors: Douglas Duane Coolbaugh, Ebenezer E. Eshun, Zhong-Xiang He, Robert Mark Rassel