Abstract: An apparatus and corresponding method for converting static data, obtained for a simulated theoretical logic circuit, into a dynamic visual display. The present invention selectively reads static simulated data produced for a theoretical logic circuit, divides the data into smaller time intervals, synchronizes the time intervals and recursively converts the data contained in each time interval into a graphical waveform image. The waveform images are recursively updated in real-time, thereby creating a dynamic visual display for the waveform.

Abstract: The present invention is a device for stabilizing tissue during surgery having an elongated sheath, a rod movable within the sheath and having a forward end capable of being extended beyond the sheath, and tissue grasping prongs located at said forward end of said rod, said prongs extending laterally away from said rod when said forward end is extended beyond the sheath for impinging and stabilizing tissue.

Abstract: The present invention provides for an improved surgical technique of the type which uses a Nd:YAG laser to treat the uterus while the uterus is kept distended by the flow of saline into the uterine cavity. The improvement comprises the hysteroscopic insertion of a retrievable ostial plug into the tubal ostia of each fallopian tube so that the saline does not flow through the fallopian tubes during the period of time in which the laser is used to treat the uterus. At the conclusion of the laser treatment, the retrievable ostial plugs are hysteroscopically retrieved and withdrawn. The invention also provides for a specific retrievable ostial plug for use in the procedure. The plugs are specifically adapted for hysteroscopic insertion and withdrawal from the tubal ostia.

Abstract: The correlator disclosed herein detects in a stream of input pulses a plurality of sequences of time spaced signals, each of the plurality of sequences having a different one of a plurality of pulse repetition intervals disposed within a given pulse repetition interval range. This is accomplished by clocking the input pulses into a first shift register by a first clock pulse having a given frequency. N groups of n bistable stages (N being an integer greater than one and n being an integer greater than zero) are disposed at different spaced time positions along the first register corresponding to the pulse repetition intervals and the pulse repetition interval range. First logic circuitry is coupled to each of the N groups of n stages to provide an output pulse when the time spaced pulses of the plurality of sequences of time spaced pulses are simultaneously present at appropriate ones of the n stages of a given number of the N groups of n stages.