Abstract: A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.

Abstract: A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.

Abstract: Probe points can be inserted (430) into an FPGA-based embedded processor SoC (305a) while specifying hardware and software cores with a design automation tool. This tool then aids the user (via high level GUI) in imbedding logic analysis functions in the SoC and connecting selected monitor signals to the logic analyzer. The design automation tool provides the necessary support files for the logic analysis software suite for naming and formatting of monitor signals on the waveform display. Trigger and trace information can be captured for the probe points and waveforms representing the captured information can be displayed (450) for analysis. An integrated logic analyzer core can be downloaded (440) into the FPGA-based embedded processor SoC to facilitate insertion of the probe points and capture of information. A software application can receive the captured information and translate it into a format suitable for display.

Abstract: A computerized method for organizing data from multiple databases into a single database for optimal access. The method includes providing multiple databases, each for storing data in the form of records. A record from each database is read, and the several records are stored in a single record within a combined database. The single record has a format such the several records are each stored in accessible portions of the single record so that they can be retrieved individually or together.

Abstract: A convergence model is shown and described for accommodating variation in data post spacing in a digital terrain elevation database (DTED) based on longitude and latitude address values for data posts. Under such a database structure, data posts lying along lines of latitude vary in spacing according to latitude, and converge at the poles with zero spacing therebetween. To scan a circular region of data posts relative to a given data post, e.g., a threat installation, this variation in data post spacing is considered by appropriately scaling sample step spacing along radials traversed in executing a radial spoke scan pattern. In this manner, a circular region of data posts surrounding a given data post may be sampled using simple, dedicated hardware despite this variation in data post spacing.

Abstract: A device executing intervisibility calculation includes a mechanism executing a radial spoke scan pattern where individual radials are traversed beginning at a threat installation and extending outward along a radial to a distance corresponding to threat range capability. Intervisibility calculation is simplified to allow implementation in a simple, dedicated hardware engine to provide rapid execution time while ensuring accurate intervisibility results. The intervisibility engine includes lookup tables to provide precalculated data and advantageously avoids divide operations whereby the intervisibility calculation may be executed by use of a series of adds, subtracts, and multiplies relative to intervisibility data developed while traversing a given radial. The engine calculates a slope for each data post visited in traversing a radial, and identifies a data post as being visible when its associated slope is greater than a previously encountered greatest magnitude slope.

Abstract: A method and apparatus for concurrently scanning and filling a memory comprised of at least a first and a second memory partition for use in a video display of the ping-pong type is provided herein. A method according to the present invention includes scanning the first memory partition and concurrently filling the second memory partition, such that a fill pattern is stored in every memory cell in the second memory partition during a time period in which a portion of memory cells in the first memory partition are scanned. A method in accordance with the invention can be incorporated into a video display system with minimal modifications to provide a fast fill or clear of a memory partition.

Abstract: A polygon tiling engine for use in a computer graphics display system. The computer graphics display system includes a high speed processor which provides lines of vertices, object type codes and START and STOP points for the vertex lines. The system further includes a VME bus. An improved apparatus for polygon tiling comprises apparatus for receiving the START and STOP points, instruction register apparatus coupled to the high speed processor for receiving instruction codes, object storing apparatus, a state machine for controlling the polygon tiling apparatus, a polygon address generating machine, a user defined object memory, a multiplexer and a triple buffered memory. Information is sent from the high speed processor to the tripled buffered memory, instruction registers and START and STOP registers. The information is processed into polygon addresses by the polygon generating apparatus. The polygon tiling apparatus is capable of tiling terrain data, multivertex polygons and user defined objects.

Abstract: An apparatus for generating three dimensional graphic symbols. Each symbol includes a plurality of polygons referenced to a datum point in a cartesian coordinate system, for example, having X, Y and Z axes. Apparatus for storing a vertex list is included. The vertex list characterizes each symbol and includes a starting address and a plurality of vertices, wherein each vertex is comprised of X, Y, and Z offsets from the datum point. In one embodiment, each vertex has a surface normal assigned to it. Connected to the vertex storing apparatus is an apparatus for registering an icon ID reference numeral to each symbol. An apparatus for mapping to the starting address is further connected to an output of the registering apparatus. The mapping apparatus uses the icon ID reference numeral to point to each symbol's starting address. Apparatus for transforming the vertex list into a different coordinate system is arranged to receive the vertex list from the vertex storing apparatus.