Abstract: In one embodiment of the present invention, a technique is provided to store and retrieve analog signals. A write circuit comprises a sampler, a circuit, and a differential amplifier. The sampler samples an input signal to generate a first sample of an input signal at a first time instant. The circuit generates a second sample which is the sampled input signal held at a second time instant. The differential amplifier generates a difference signal representing a difference between the first sample and the second sample. The difference signal is stored in a multilevel storage array. A read circuit comprises a sample-and-hold device, a summing amplifier, and a circuit. The sample-and-hold device is coupled to a multilevel storage array to generate a first sample stored in the multilevel storage array at a first time instant. The summing amplifier generates a sum signal representing a sum between the first sample and a second sample. The circuit generates the second sample at a second time instant.

Abstract: In one embodiment of the present invention, a technique is provided to store and retrieve analog signals. A write circuit comprises a sampler, a circuit, and a differential amplifier. The sampler samples an input signal to generate a first sample of an input signal at a first time instant. The circuit generates a second sample which is the sampled input signal held at a second time instant. The differential amplifier generates a difference signal representing a difference between the first sample and the second sample. The difference signal is stored in a multilevel storage array. A read circuit comprises a sample-and-hold device, a summing amplifier, and a circuit. The sample-and-hold device is coupled to a multilevel storage array to generate a first sample stored in the multilevel storage array at a first time instant. The summing amplifier generates a sum signal representing a sum between the first sample and a second sample. The circuit generates the second sample at a second time instant.

Abstract: A calling party announcement apparatus and method for providing the identity of the caller in a non-synthesized, pre-recorded human speech. The invention detects and decodes the Incoming Caller Line Identification (ICLID) signal between ring signals before the called party answers the phone and announces the calling party's name and/or phone number. The called party answers the telephone or rejects the call before the receiver goes off-hook. Additionally, if the called party elects to accept the call, the call is answered, an individualized pre-recorded message is played back, or any other preferences selected with respect to the ICLID information is performed. An important aspect of the invention is the ability to play and record announcements and messages without the use of expensive and power-consuming digital signal processors. The invention provides for recording and locating pre-recorded announcements and predetermined preferences for call acceptance using the decoded ICLID information.

Abstract: An initializing circuit and protection circuit for MOS integrated circuits which employ substrate biasing are disclosed. In one embodiment, a weak depletion mode transistor is coupled between a line in the integrated circuit and ground. The gate of this transistor receives the substrate biasing potential. Since this transistor is enabled without power applied to the circuit, when the circuit is powered-up, this transistor effectively shorts-out the line and prevents the transmission of stray signals. When the substrate biasing potential is reached, the transistor is disabled and effectively removed from the circuit. Once this occurs, normal transmissions on the line are possible.

Abstract: An integrated circuit watch which employs a RAM and PLA to execute its timekeeping functions can be significantly improved to include a multiplicity of zones without entailing greater complexity of circuitry or large amounts of chip space and may incorporate user programmability by incorporation of the present invention. The number of independent and distinct watch functions within the integrated circuit watch can be increased by coupling a flag RAM to the main PLA. The flag bits, which are associated with the counting states of each separate watch function are then accessibily stored within the flag RAM and appropriately coupled to the main PLA to execute the required timekeeping operation at the appropriate time. A processor is coupled to the flag RAM and may selectively process or manipulate each of the flag bits in the flag RAM in response to instructions or control signals, some of which may be user initiated.