Abstract: An aircraft control system improves system flexibility, scalability, redundancy, and separation. The system uses a "virtual backplane" architecture which maximizes system flexibility and scalability and allows easy integration of new functions. The architecture comprises four major elements: processing modules; input and output modules (i.e. I/O modules); database modules; and an aircraft wide system network. Inter module communication occurs via the aircraft wide system network thereby eliminating the need for point to point communication and making modules independent of physical location or what modular units (MUs) they are in. Predetermined periodic and deterministic broadcast techniques improve the safety and communications efficiency of the system.

Abstract: A channel of an automatic flight control system utilizes dual identical digital processors. Active task modules and monitor modules therefor are included in the processors. The active task modules and the monitor modules are arranged so that an active task module in one processor has a corresponding monitor module in the other processor where the corresponding modules perform disparate functionality over disjoint computation paths with respect to each other. The monitor module tests to determine if the aircraft is performing in a manner prohibited by the functionality controlled by the associated task module.

Abstract: An automatic flight control system having two digital processors receives sensor data over a bit serial data bus through a serial-to-parallel converter. The converter formats the data into bytes corresponding to the data parameters from the sensors. One of the processors controls the bus timing and receives the data bytes which are simultaneously applied to an independent data storage element. An independent address sequencer provides sequential addresses to the independent data storage element at which to store sequential data bytes from the converter. After an entire data frame is stored in the independent data storage element, the second processor performs a bulk move of the data into its local data storage element. The sensors are configured in data subsystems which provide respective messages, each message containing an address identifying the subsystem. These addresses are utilized for directing the data messages to respective areas in the independent data storage element.