Abstract: In a component video signal to composite video signal encoding system (10), the component input signals are stored in a first in, first out (FIFO) memory. The FIFO memory is connected by 1 luminance and 2 chrominance outputs to a rate converter, which increases the digital sampling rate of the signals as received from the FIFO memory. The rate converter is in turn connected by 1 luminance and 2 chrominance outputs to luminance and chrominance processing circuits. The luminance and chrominance processing circuits produce the composite video signals, and are connected to a D2 standard driver circuit. The output of the D2 driver circuit is D2 standard digital component signals. The luminance and chrominance processing circuits are also connected to a digital to analog (D/A) converter. The output of the D/A converter is an analog PAL or NTSC component video signal.

Abstract: A digital still store system (10) receives composite digital 4:2:2 D1 video signal inputs in parallel at (12) or serially at (14). The signals are supplied in component form selectively to one of framestores (18) and (20). The component signals are supplied from the framestores (18) and (20) to hard disks (22) through a buffer store (24) and disk input/output (I/O) circuits (26). Each of the hard disks (22) stores still video images as either 525 or 625 line digital frames for either NTSC or PAL composite signal inputs and outputs. Y and C fields of component video signal information are supplied from the hard disks (22) through the buffer store (24) and one of the frame stores 18 and 20 to a compositor (28) for output as digital 4:2:2 video signals. The buffer store (24) obtains the video signal fields for either full size images or 1/4 size images, when an array for browsing and selection is desired.

Abstract: A real-time disk system (10) stores and plays back D1 digital 10-bit 4:2:2 component video and audio signals from magnetic storage disks (12). The system (10) has a main channel subsystem (14) with an associated smooth motion option (16) and a second or key channel option subsystem (18) with an associated smooth motion option (20). Serial and parallel D1 digital video inputs (30) and (32) and outputs (34) and (36) are connected to each of the channels (14) and (18) and to control subsystem (22). In the main channel (14), the serial and parallel D1 input (30) is connected through an input board (60) to a video processing board (62). The video board (62) is connected by a bidirectional, 11.times.2 wide bus (64) to disk arrays (66) and (68). Digital video signal information is stored and retrieved in parallel to and from the disk arrays (66) and (68) without requiring any serial to parallel or parallel to serial conversion.

Abstract: A decoding system (10) receives a composite digital NTSC D2 input signal or a composite analog NTSC RS-170A input signal. The decoding system (10) decodes and sample rate converts to a component digital D1 output and a component analog RGB or Y(R-Y) (B-Y) output. A control panel (20) is connected to the decoding system (10) to provide digital control of the important decoding parameters to provide decoding flexibility. The composite video signal is supplied directly to an adaptive combiner (44), through a line comb filter (48) to the adaptive combiner (44), and through a frame comb filter (52) to the adaptive combiner (44). The composite video signal is also supplied to a frame transition or motion detector (58) and to a line transition or motion detector (60). If no frame transition or motion is detected, the adaptive combiner (44) utilizes frame based three dimensional decoding.