Abstract: An apparatus and method for providing short circuit current free dynamic logic building blocks comprising P-logic and N-logic dynamic domino building blocks having separate clocks for driving the P-logic and N-logic evaluate and pre-charge stages. The P-logic building gates are pre-charged to a zero volt output and upon the transition from high to low on the input line, will provide a high output during the evaluation cycle. Conversely, the N-logic building blocks are pre-charged with a high output level and upon the transition of a low to high input to the building block device, will provide a low output signal during the evaluation period. Both building block types are pre-charged again at the end of the evaluation period to provide an inherently glitch-free dynamic logic device. Separate evaluate and charge clock signals are provided to each of the P-logic and N-logic building blocks which are configured to provide a non-overlapping charge and evaluation cycle.

Abstract: A modulo addition circuit generates a sequence of values within a specified range having a lower bound value and an upper bound value. The modulo addition circuit generates a first value by adding a displacement value to a previously defined starting value, and generates a second value by adding to or subtracting from the first generated value a modulo value. Both the first and second values are generated in a single computational cycle using a single address circuit. When the first generated value is in the range defined the lower bound and upper bound values, the modulo addition circuit outputs the first value; otherwise the modulo addition circuit outputs the second generated value. The value output by the modulo addition circuit is stored in a register so as to be available as the starting value in a next computational cycle.