Abstract: Various implementations described herein refer to a device having a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first network that links nodes together in the first layer. The device may have a second network that links the nodes in the first layer together by way of the second layer so as to reduce latency related to data transfer between the nodes.

Abstract: There is provided, in a parallel pipelined structure on a multi-core device, a method for parallel pipelined multi-core indexing. The method includes generating one or more single document indexes respectively corresponding to one or more single documents of a given data stream. The method further includes generating one or more multi-document interval-based hash tables from the one or more single document indexes. The method also includes generating a global hash table formed from merging one or more of the multi-document interval-based hash tables, the global hash table representing a collective index for all of the single documents for which the one or more single document indexes were generated.

Abstract: A structure formation method. The method may include: attaching a substrate, a first interposer, a second interposer, and a first bridge together such that the first interposer is on and electrically connected to the substrate, the second interposer is on and electrically connected to the substrate, the first interposer comprises at least a first transistor, and the second interposer comprises at least a second transistor. The method may alternatively include: disposing both a first and second interposer on a substrate, wherein the first and second interposer are each electrically connected to the substrate; and electrically connecting a first bridge to the first and second interposers, wherein (i) the first bridge is in direct physical contact with the substrate or (ii) a bottom surface of the first bridge is within the substrate and below a top surface of the substrate.

Abstract: A structure formation method. The method may include: attaching a substrate, a first interposer, a second interposer, and a first bridge together such that the first interposer is on and electrically connected to the substrate, the second interposer is on and electrically connected to the substrate, the first interposer comprises at least a first transistor, and the second interposer comprises at least a second transistor. The method may alternatively include: disposing both a first and second interposer on a substrate, wherein the first and second interposer are each electrically connected to the substrate; and electrically connecting a first bridge to the first and second interposers, wherein (i) the first bridge is in direct physical contact with the substrate or (ii) a bottom surface of the first bridge is within the substrate and below a top surface of the substrate.

Abstract: A structure and a method for forming the same. The structure includes a substrate, a first interposer on the substrate, a second interposer on the substrate, and a first bridge. The first and second interposers are electrically connected to the substrate. The first bridge is electrically connected to the first and second interposers.

Abstract: There is provided, in a parallel pipelined structure on a multi-core device, a method for parallel pipelined multi-core indexing. The method includes generating one or more single document indexes respectively corresponding to one or more single documents of a given data stream. The method further includes generating one or more multi-document interval-based hash tables from the one or more single document indexes. The method also includes generating a global hash table formed from merging one or more of the multi-document interval-based hash tables, the global hash table representing a collective index for all of the single documents for which the one or more single document indexes were generated.

Abstract: A structure and a method for forming the same. The structure includes a substrate, a first interposer on the substrate, a second interposer on the substrate, and a first bridge. The first and second interposers are electrically connected to the substrate. The first bridge is electrically connected to the first and second interposers.

Abstract: A method and apparatus for sharing memory in a multiprocessor computing system. More specifically, this invention provides a number of system buses with each bus being connected to a respective memory controller which controls a corresponding partition of the memory. Any one of the processors can use any one of the system buses to send real addresses to the connected memory controller which then converts the real addresses into physical addresses corresponding to the partition of memory that is controlled by the receiving memory controller. The processors can be dynamically assigned to different partitions of the memory by via a switching mechanism.

Abstract: A method, system, and associated program code and data structures are provided for a message processing system in which messages are passed from source nodes to destination nodes. Notification of the arrival of the messages at the destination nodes can be effected by programmable source initiated interrupts or destination initiated interrupts. The source initiated interrupts are implemented as set fields embedded in the message packets sent from a source node to a destination node and trigger the requisite interrupt at the destination node upon message arrival. The destination initiated interrupts are implemented as pre-set fields in anticipatory buffers which are allocated at the destination node for incoming messages from the source node. Standard incoming message queue polling, as well as interrupt enabling and disabling functions are also provided, which together allow the system to selectively invoke interrupt or alternative strategies to notify destination nodes of arriving messages.

Abstract: A method, system, and associated program code and data structures are provided for a message processing system in which messages are passed from source nodes to destination nodes. Notification of the arrival of the messages at the destination nodes can be effected by programmable source initiated interrupts or destination initiated interrupts. The source initiated interrupts are implemented as set fields embedded in the message packets sent from a source node to a destination node and trigger the requisite interrupt at the destination node upon message arrival. The destination initiated interrupts are implemented as pre-set fields in anticipatory buffers which are allocated at the destination node for incoming messages from the source node. Standard incoming message queue polling, as well as interrupt enabling and disabling functions are also provided, which together allow the system to selectively invoke interrupt or alternative strategies to notify destination nodes of arriving messages.

Abstract: A method, system, and associated program code and data structures are provided for a message processing system in which messages are passed from source nodes to destination nodes. Notification of the arrival of the messages at the destination nodes can be effected by programmable source initiated interrupts or destination initiated interrupts. The source initiated interrupts are implemented as set fields embedded in the message packets sent from a source node to a destination node and trigger the requisite interrupt at the destination node upon message arrival. The destination initiated interrupts are implemented as pre-set fields in anticipatory buffers which are allocated at the destination node for incoming messages from the source node. Standard incoming message queue polling, as well as interrupt enabling and disabling functions are also provided, which together allow the system to selectively invoke interrupt or alternative strategies to notify destination nodes of arriving messages.

Abstract: A memoryless communications adapter for communicating between the nodes of a distributed parallel computer network, each node including a non-shared program memory coupled to the memoryless communications adapter which interfaces the network. An embodiment of the present invention advantageously provides an adapter that can manipulate queues and matching tables efficiently in hardware and provide a high-level object view of queues and matching in the context of communication between nodes. Preferably, the Queue manipulation logic, Match Table manipulation logic and the Sequence Table manipulation logic are implemented in the adapter hardware which does not keep any state or resources in it that depend on the size of the system or the number of queues/tables instantiated. The actual states of these objects may be kept in the program memory, so that the adapter hardware is memoryless.