Patents by Inventor Douglas Joseph Lange

Douglas Joseph Lange has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6831329
    Abstract: A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: December 14, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Jon Gladish, Sampat Shekhawat, Gary M. Dolny, Praveen Muraleedharan Shenoy, Douglas Joseph Lange, Mark L. Rinehimer
  • Publication number: 20030080377
    Abstract: A quick punch-through integrated gate bipolar transistor (IGBT) includes a drift region and a gate. The drift region has a drift region dopant concentration and a drift region thickness. The gate has a gate capacitance. The drift region dopant concentration, drift region thickness and gate capacitance are adjusted dependent at least in part upon the PNP gain of the IGBT to maintain the potential difference between the gate and emitter at a level greater than the IGBT threshold voltage when the collector voltage reaches the bus voltage. This insures that the hole carrier concentration remains approximately equal to or greater than the drift region dopant concentration when the depletion layer punches through to the buffer region during the turn-off delay. Thus, the collector voltage overshoot and the rate of change of voltage and current are controlled, and electromagnetic interference is reduced, during turn off.
    Type: Application
    Filed: October 22, 2002
    Publication date: May 1, 2003
    Inventors: Joseph A. Yedinak, Jon Gladish, Sampat Shekhawat, Gary M. Dolny, Praveen Muraleedharan Shenoy, Douglas Joseph Lange, Mark L. Rinehimer