Abstract: S-doped SnO2 nanoparticles are synthesized by a solid-state process where thermal vaporization of sulfur powder under inert atmosphere to partially sulfurize the SnO2 nanoparticles. In the catalyst, the sulfur concentration is between 0.1 to 2 at%. A catalyst ink can be prepared from the catalyst containing: a liquid carrier; conductive particles; optionally an ionomer, and the catalyst. A gas diffusion electrode comprising the S-SnO2 catalyst dispersed onto a carbon paper electrode is also described.

Abstract: A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

Abstract: A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

Abstract: A method and an apparatus are provided for post-layout optimization of an integrated circuit. In one instance, only local transformations accomplished by incremental changes to placement and routing are provided, so as to avoid the costly design iteration loop that requires re-synthesis, re-place and re-route. Optimization can be provided in multiple optimization phases each accomplishing a specified set of transformations. Static timing analysis is performed at the end of each set of local transformations to determine if further optimization steps are required. In one instance, the physical design is first scanned for mismatch between drivers and loads. Then, in a second optimization phase, “hot spots” in the physical design are identified for local transformation using a “bidirectional combinational total negative slack” (BCTNS) algorithm. In subsequent phases, optimization based on meeting setup times and hold times in a critical path are performed.

Abstract: A comprehensive system and method allow an integrated circuit designer to extract accurate estimates of parasitic impedances in interconnection lines of an integrated circuit. The method includes collecting values of electrical characteristic parameters to provide a technology profile for a particular fabrication process. An Interconnect Primitive Library builder provides a collection of interconnect `primitives` that any interconnect structure fabricated under the fabrication process can be broken down into, and combines it with the technology profile for simulations in a 3-dimensional field solver to extract parameterized coupling capacitances and other characteristic impedances for each interconnect primitive. An extraction tool traces a signal path of an integrated circuit and decomposes the interconnect structures on the signal path into interconnect primitives and maps them to the Interconnect Primitive Library.