Abstract: A memory having a plurality of word locations, each having a bit location, includes a parity word in one of the word locations. Bit selector means selects a column of bits made up of like positioned bits in each of the word locations. All bits in a column are added together to indicate whether there is a successful parity check. Each such column is successively checked thereby verifying the integrity of the stored information on a column basis.

Abstract: A memory in a device controller divided into sections which are equal in number to the potential number of devices controllable by the controller, each section having a plurality of storage locations for storing the same topology of information in like positioned locations in the other sections is provided, such information including control and status indicators. Apparatus for addressing the locations independent of the addressing of the sections is provided, the sections being addressable independent of the active device or under normal conditions in direct relationship to the identity of the active device so that the information in one section may be changed even though a device associated with another section is then active.

Abstract: Different type devices coupled at random to different channels of a controller therefor, are identified and initial conditions are set by successively comparing known identification codes provided by the controller for known devices with the unknown identification code received from the device whose channel is enabled. In response to positive comparison the identity of the device is known and the controller provides a stored record of such identity and further enables device type specific operations to be provided by the controller.

Abstract: A device controller having a microprogrammed control store for storing instructions useable in the control of the controller and a scratch pad memory for storing device specific information useable in the control and operation of the device is provided. An addressed instruction is received by an instruction register from which control signals are generated. The contents of the instruction register are used to address the control store as well as the scratch pad memory and in addition is received by means of a multiplexor by an arithmetic unit which provides computations in the controller. The multiplexor which in addition receives signals from the scratch pad memory and the devices is also directly coupled to write information in the scratch pad memory. The controller may receive diagnostic and other instructions from a coupled data processor which are then used to control the operation of the controller in place of the instructions in the control store.

Abstract: In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus during asynchronously generated information bus transfer cycles, the units are coupled in a priority network and depending upon their respective priority may gain access to the bus before a lower priority unit is so enabled. Each one of the units includes apparatus for responding to a request for the transfer of information from another unit by providing any one of up to three signal responses including a positive acknowledge signal indicating an immediate response, a negative acknowledge signal indicating that the unit will most likely be busy for a relatively extended period of time and a quasi-negative response indicating that the unit will probably be ready during the next asynchronously generated bus transfer cycle.