Abstract: A redundant array of independent disk (RAID) stack executes a first memory access routine and a second memory access routine having different access timing characteristics. The RAID stack determines a number of cache misses for the execution of each of the first and second memory access routines. The RAID stack selects one of the first and second memory access routines based on the number of cache misses for further memory accesses.

Abstract: A redundant array of independent disk (RAID) stack executes a first memory access routine and a second memory access routine having different access timing characteristics. The RAID stack determines a number of cache misses for the execution of each of the first and second memory access routines. The RAID stack selects one of the first and second memory access routines based on the number of cache misses for further memory accesses.

Abstract: A redundant array of independent disk (RAID) stack determines a first number of processor cycles to reload first data from a first memory address of a main memory into a processor of a data processing system. The RAID stack loads second data from a second memory address of the main memory into the processor, where the second memory address is configured to be an address offset from the first memory address. The RAID stack reloads the first data from the first memory address of the main memory and determines a second number of processor cycles to reload the first data from the first memory address of the main memory. An alias offset of a cache memory associated with the processor of the data processing system is determined based on the first number of processor cycles and the second number of processor cycle.

Abstract: For each of a plurality of memory access routines having different access timing characteristic, a redundant array of independent disk (RAID) stack executes the memory access routine to load predetermined data from a main memory to a register of a processor of a data processing system. The RAID stack determines an amount of cache misses for the execution of the memory access routine. The RAID stack selects one of the plurality of memory access routines that has the least amount of cache misses for further memory accesses for the purpose of parity calculations of RAID data.

Abstract: A redundant array of independent disk (RAID) stack loads a first parity block of RAID data into a first memory address of a main memory of a data processing system. A first parity calculation is performed on a first plurality of data blocks of the RAID data with the first parity block loaded from the first memory address of the main memory into a register of the processor of the data processing system and a cache memory associated with the processor. The RAID stack loads subsequent parity blocks of RAID data into subsequent memory addresses of the main memory, where a difference between the first memory address and the subsequent memory addresses equals to one or more multiples of an alias offset associated with the cache memory. A second parity calculation is performed on a second plurality of data blocks and the second parity block of the RAID data.

Abstract: A redundant array of independent disk (RAID) stack loads a parity block of RAID data from a main memory into a first register of a processing device and loading the parity block into a cache memory of the processing device. The RAID stack loads a first data block of the RAID data from the main memory into a second register of the processing device without loading the first data block into the cache memory of the processing device. The processing device performs a first parity calculation based on the parity block of the first register and the first data block of the second register.

Abstract: For each of a plurality of memory access routines having different access timing characteristic, a redundant array of independent disk (RAID) stack executes the memory access routine to load predetermined data from a main memory to a register of a processor of a data processing system. The RAID stack determines an amount of cache misses for the execution of the memory access routine. The RAID stack selects one of the plurality of memory access routines that has the least amount of cache misses for further memory accesses for the purpose of parity calculations of RAID data.

Abstract: A redundant array of independent disk (RAID) stack determines a first number of processor cycles to reload first data from a first memory address of a main memory into a processor of a data processing system. The RAID stack loads second data from a second memory address of the main memory into the processor, where the second memory address is configured to be an address offset from the first memory address. The RAID stack reloads the first data from the first memory address of the main memory and determines a second number of processor cycles to reload the first data from the first memory address of the main memory. An alias offset of a cache memory associated with the processor of the data processing system is determined based on the first number of processor cycles and the second number of processor cycle.

Abstract: A redundant array of independent disk (RAID) stack loads a first parity block of RAID data into a first memory address of a main memory of a data processing system. A first parity calculation is performed on a first plurality of data blocks of the RAID data with the first parity block loaded from the first memory address of the main memory into a register of the processor of the data processing system and a cache memory associated with the processor. The RAID stack loads subsequent parity blocks of RAID data into subsequent memory addresses of the main memory, where a difference between the first memory address and the subsequent memory addresses equals to one or more multiples of an alias offset associated with the cache memory. A second parity calculation is performed on a second plurality of data blocks and the second parity block of the RAID data.

Abstract: A redundant array of independent disk (RAID) stack loads a parity block of RAID data from a main memory into a first register of a processing device and loading the parity block into a cache memory of the processing device. The RAID stack loads a first data block of the RAID data from the main memory into a second register of the processing device without loading the first data block into the cache memory of the processing device. The processing device performs a first parity calculation based on the parity block of the first register and the first data block of the second register.