Abstract: The system and method of this invention classifies the options of a data processing system into test levels based upon the dependency of the option to other options within a configuration of the processing system. The test level information for each option is stored in a present configuration list of the options. In addition, prerequisite rule bases are linked to each dependent option in the configuration list. The diagnostic system accesses the test level information and the prerequisite rule base information to determine when to test an option, and the order in which to test options, when isolating a failing option. A failing option can be isolated during a system checkout, a selected option checkout, or by resolving a missing option in the present configuration.

Abstract: A communication system is provided in which one data transmitting display terminal has the capability of transmitting a data stream in coded form to at least one data receiving terminal over a communication linkage. This data transmitting terminal further includes the capability of displaying, when necessary, the stream of coded data directly on its display so that if there is a transmission problem, the coded data itself can be analyzed in diagnosing the problem.The present communications system has the further capability of diagnosing data streams at remote display terminals. For example, if one transmitting terminal is communicating with a receiving terminal and a problem arises between the two terminals, the system provides the capability of the transmitting terminal sending the data stream to another receiving terminal remote from the first two terminals.

Abstract: A communication adapter circuit (10) is connected to a processor through a data bus (12)and a control bus (14). Data and control signals are provided through the buses (12,14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24). Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry. A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10). From the control circuits (22, 24) the data is transmitted through a bi-directional serial line (44) to a dual modem switch (56). From the switch (56) the data is transmitted to either an EIA interface circuit (60) to a conventional modem or through a line (64) to an internal modem.