Abstract: A first pair of resistors formed in a first layer of material, and a second pair of resistors formed in the first layer or in a second layer can be wired into a Wheatstone bridge to form a temperature sensor. Either layer can include a semiconductor or a dielectric. In a semiconductor layer, a pair of resistors can be doped areas of the layer, while in a dielectric, a pair of resistors can be material deposited in cavities in the layer, such as material from an added “middle-of-line” (MOL) metallization layer.

Abstract: Methods of fabricating an on-chip capacitor with a variable capacitance, as well as methods of adjusting the capacitance of an on-chip capacitor and design structures for an on-chip capacitor. The method includes forming first and second ports configured to be powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. The method includes configuring the first voltage-controlled unit to selectively couple the first electrode with the first port, and the second voltage-controlled unit to selectively couple the second electrode with the second port. When the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port, the capacitance of the on-chip capacitor increases.

Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.

Abstract: Stacked chip systems and design structures for stacked chip systems, as well as methods and computer program products for placing thermal conduction paths in a stacked chip system. The method may include determining an availability of space in a layout of an interconnect structure of a first chip for a fill shape structure extending partially through the interconnect structure to thermally couple a metal feature in the interconnect structure with a bonding layer between the interconnect structure of the first chip and a second chip. If space is available, the fill shape structure may be placed in the layout of the interconnect structure of the first chip. The stacked chip system may include the first and second chips, the bonding layer between the interconnect structure of the first chip and the second chip, and the fill shape structure.

Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap.

Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap. The third band gap is configured to bend under an external bias to assist in aligning a first energy band of the first semiconductor material with a second energy band of the second semiconductor material.

Abstract: Device structures, fabrication methods, and design structures for tunnel field-effect transistors. A drain comprised of a first semiconductor material having a first band gap and a source comprised of a second semiconductor material having a second band gap are formed. A tunnel barrier is formed between the source and the drain. The second semiconductor material exhibits a broken-gap energy band alignment with the first semiconductor material. The tunnel barrier is comprised of a third semiconductor material with a third band gap larger than the first band gap and larger than the second band gap.

Abstract: A first pair of resistors formed in a first layer of material, and a second pair of resistors formed in the first layer or in a second layer can be wired into a Wheatstone bridge to form a temperature sensor. Either layer can include a semiconductor or a dielectric. In a semiconductor layer, a pair of resistors can be doped areas of the layer, while in a dielectric, a pair of resistors can be material deposited in cavities in the layer, such as material from an added “middle-of-line” (MOL) metallization layer.

Abstract: Methods of fabricating an on-chip capacitor with a variable capacitance, as well as methods of adjusting the capacitance of an on-chip capacitor and design structures for an on-chip capacitor. The method includes forming first and second ports configured to be powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. The method includes configuring the first voltage-controlled unit to selectively couple the first electrode with the first port, and the second voltage-controlled unit to selectively couple the second electrode with the second port. When the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port, the capacitance of the on-chip capacitor increases.

Abstract: Stacked chip systems and design structures for stacked chip systems, as well as methods and computer program products for placing thermal conduction paths in a stacked chip system. The method may include determining an availability of space in a layout of an interconnect structure of a first chip for a fill shape structure extending partially through the interconnect structure to thermally couple a metal feature in the interconnect structure with a bonding layer between the interconnect structure of the first chip and a second chip. If space is available, the fill shape structure may be placed in the layout of the interconnect structure of the first chip. The stacked chip system may include the first and second chips, the bonding layer between the interconnect structure of the first chip and the second chip, and the fill shape structure.

Abstract: Methods of fabricating an on-chip capacitor with a variable capacitance, as well as methods of adjusting the capacitance of an on-chip capacitor and design structures for an on-chip capacitor. The method includes forming first and second ports configured to be powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. The method includes configuring the first voltage-controlled unit to selectively couple the first electrode with the first port, and the second voltage-controlled unit to selectively couple the second electrode with the second port. When the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port, the capacitance of the on-chip capacitor increases.

Abstract: Methods of fabricating an on-chip capacitor with a variable capacitance, as well as methods of adjusting the capacitance of an on-chip capacitor and design structures for an on-chip capacitor. The method includes forming first and second ports configured to be powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. The method includes configuring the first voltage-controlled unit to selectively couple the first electrode with the first port, and the second voltage-controlled unit to selectively couple the second electrode with the second port. When the first electrode is coupled by the first voltage-controlled unit with the first port and the second electrode is coupled by the second voltage-controlled unit with the second port, the capacitance of the on-chip capacitor increases.

Abstract: On-chip capacitors with a variable capacitance, as well as design structures for a radio frequency integrated circuit, and method of fabricating and method of tuning on-chip capacitors. The on-chip capacitor includes first and second ports powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. Each of the first and second voltage-controlled units is switched between a first state in which the first and second electrodes are electrically isolated from the first and second ports and a second state. When the first voltage-controlled unit is switched to the second state, the first electrode is electrically connected with the first port. When the second voltage-controlled unit is switched to the second state the second electrode is electrically connected with the second port. The on-chip capacitor has a larger capacitance value when the first and second voltage-controlled units are in the second state.

Abstract: Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor.

Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure that includes an on-chip inductor and an on-chip capacitor, as well as methods for tuning and fabricating a resonator that includes the on-chip inductor and on-chip capacitor. The fabrication methods generally include forming the on-chip capacitor and on-chip inductor in different metallization levels of the BEOL wiring structure and laterally positioned to be substantially vertical alignment. The on-chip capacitor may serve as a Faraday shield for the on-chip inductor. Optionally, a Faraday shield may be fabricated either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the directly-connected electrodes of the on-chip capacitor for tuning, during circuit operation, a resonance frequency of an LC resonator that further includes the on-chip inductor.

Abstract: On-chip capacitors with a variable capacitance, as well as design structures for a radio frequency integrated circuit, and method of fabricating and method of tuning on-chip capacitors. The on-chip capacitor includes first and second ports powered with opposite polarities, first and second electrodes, and first and second voltage-controlled units. Each of the first and second voltage-controlled units is switched between a first state in which the first and second electrodes are electrically isolated from the first and second ports and a second state. When the first voltage-controlled unit is switched to the second state, the first electrode is electrically connected with the first port. When the second voltage-controlled unit is switched to the second state the second electrode is electrically connected with the second port. The on-chip capacitor has a larger capacitance value when the first and second voltage-controlled units are in the second state.

Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure that includes an on-chip inductor and an on-chip capacitor, as well as methods for tuning and fabricating a resonator that includes the on-chip inductor and on-chip capacitor. The fabrication methods generally include forming the on-chip capacitor and on-chip inductor in different metallization levels of the BEOL wiring structure and laterally positioned to be substantially vertical alignment. The on-chip capacitor may serve as a Faraday shield for the on-chip inductor. Optionally, a Faraday shield may be fabricated either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the directly-connected electrodes of the on-chip capacitor for tuning, during circuit operation, a resonance frequency of an LC resonator that further includes the on-chip inductor.

Abstract: Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor.