Patents by Inventor Douglas P. Sheppard
Douglas P. Sheppard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8964451Abstract: A memory cell system/method incorporating reduced transistor counts and/or improved design-for-manufacturability (DFM) is disclosed. The system/method incorporates cross-coupled feedthru (3410)/feedback (3420) amplifiers to implement memory cell state memory, wherein the feedback amplifier incorporates a multi-state output drive capability (3423) allowing the memory cell to be read/written using only one access device (3430) connected to the output (3412) of the feedthru (3410) amplifier. The multi-state output drive capability (3423) modulates the feedback amplifier (3420) drive strength to enable reading/writing of the feedthru amplifier (3410) state with greatly reduced memory cell input fan-in requirements. The invention anticipates replacement of traditional DP/8T/6T/4T memory cell structures with corresponding 6T/6T/5T/3T memory cell configurations, resulting in a 16%-25% transistor reduction depending on memory array application context.Type: GrantFiled: March 9, 2012Date of Patent: February 24, 2015Inventor: Douglas P. Sheppard
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Publication number: 20120230130Abstract: A memory cell system/method incorporating reduced transistor counts and/or improved design-for-manufacturability (DFM) is disclosed. The system/method incorporates cross-coupled feedthru (3410)/feedback (3420) amplifiers to implement memory cell state memory, wherein the feedback amplifier incorporates a multi-state output drive capability (3423) allowing the memory cell to be read/written using only one access device (3430) connected to the output (3412) of the feedthru (3410) amplifier. The multi-state output drive capability (3423) modulates the feedback amplifier (3420) drive strength to enable reading/writing of the feedthru amplifier (3410) state with greatly reduced memory cell input fan-in requirements. The invention anticipates replacement of traditional DP/8T/6T/4T memory cell structures with corresponding 6T/6T/5T/3T memory cell configurations, resulting in a 16%-25% transistor reduction depending on memory array application context.Type: ApplicationFiled: March 9, 2012Publication date: September 13, 2012Inventor: Douglas P. Sheppard
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Patent number: 7092279Abstract: A memory array employing shared bit-lines. A memory is formed from an array of plural bit-cells organized as plural columns and plural rows. Plural word-lines are aligned with each for the rows, and each is electrically coupled to a discrete fraction of the bit-cells its corresponding row. The memory also includes plural bit-lines that are aligned with the plural columns. Every bit-line is electrically coupled to all of the bit-cells that lie along at least one column. In addition, at least a first one of the bit-lines is further electrically coupled to all of the bit-cells in an additional column. That bit-line is coupled such that every one of the plural bit-cells, that lie along any given row that are coupled to it, is coupled to a unique word-line from the other bit-cells coupled thereto. The shared bit-line invention is applicable to single and multiple port memory arrays. It is applicable to all memory array technologies including, but not limited to, SRAMs and DRAMs.Type: GrantFiled: September 29, 2004Date of Patent: August 15, 2006Inventor: Douglas P. Sheppard
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Patent number: 7050345Abstract: A memory device and method with reduced power consumption and improved noise performance. An illustrative embodiment provides a random access memory with an array of plural memory bit cells, having bit-latches coupled between bit-true pass-gates and bit-compliment pass-gates are organized as plural columns and rows. There are plural bit lines pairs aligned with the plural columns, each of the bit line pairs including a bit-true and a bit-compliment bit line. The bit cell pass-gates are electrically coupled to a bit-true and a bit-compliment line pair along each particular column. Plural word lines are aligned with the plural rows, each of the rows having an integer number, greater than one, of word lines aligned therewith. Each one of the integer numbers of word lines is electrically coupled to a fraction of the bit cells in its aligned row.Type: GrantFiled: July 29, 2004Date of Patent: May 23, 2006Inventor: Douglas P. Sheppard
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Patent number: 5715197Abstract: A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port configurations, thereby reducing the number of combinations necessary in a standard cell library or gate array to implement the every possible configuration. In one embodiment of the invention, a dual port RAM is provided with a decoder, an input multiplexer and an output multiplexer for each data port. The input multiplexer for each data port provides several different selectable mappings of a RAM input word of varying sizes to the input bit lines of the respective data port. Similarly, the output multiplexer for each data port provides several different selectable mappings of the RAM output bit lines to the RAM output word.Type: GrantFiled: July 29, 1996Date of Patent: February 3, 1998Assignee: Xilinx, Inc.Inventors: Scott S. Nance, Douglas P. Sheppard, Nicholas J. Sawyer
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Patent number: 5124577Abstract: A circuit for presetting the voltage of an output terminal connected to an external load, where the output terminal receives either a high or a low voltage level state for output to the load during a data cycle, includes a voltage detector connected to the output terminal for sensing the voltage level at the output terminal at the end of the data cycle to determine whether the voltage level is at a high or a low voltage level state. A driver is connected to the voltage sensor for driving the voltage level at the output terminal prior to the start of a subsequent data cycle toward the opposite voltage state to a mid-level, as determined by the prior voltage state sensed by the voltage detector.Type: GrantFiled: September 28, 1990Date of Patent: June 23, 1992Assignees: Benchmarq Microelectronics, Inc., NEC CorporationInventors: Harold L. Davis, Douglas P. Sheppard
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Patent number: 4646306Abstract: A high speed parity circuit uses a sequence of simplified exclusive-OR circuits responsive to data input terminals containing a data signal and its complement and terminating in a sense amplifier, together with an operating sequence in which the inputs to the sequence are grounded while the data lines are first brought high and then set to the correct data state to form a pair of separate paths through the sequence when no current flows, after which set-up operation an input voltage circuit raises the voltage on one of the paths smoothly, so that the sense amplifier can respond as soon as its input is large enough, without waiting for a settling time.Type: GrantFiled: December 26, 1984Date of Patent: February 24, 1987Assignee: Thomson Components - Mostek CorporationInventors: Harold L. Davis, Douglas P. Sheppard
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Patent number: 4495602Abstract: A read only memory circuit (10) includes an array of memory transistors including a row of such transistors (12-28) connected to a common word line (30). For each column of memory transistors there is provided a set of reference transistors which receive a word line signal which is concurrent with any word line signal provided to any word line in the memory array. Column decode signals (CD1-CD4) are provided to select a memory transistor on an activated word line and to select corresponding reference transistors. The memory transistor is fabricated to have one of a plurality of threshold voltages. The reference transistors are fabricated to have different predetermined threshold voltages. The drive signals are applied through the word lines concurrently to the selected memory transistor and corresponding reference transistors to cause the transistors to transition from a first state to a second state.Type: GrantFiled: December 28, 1981Date of Patent: January 22, 1985Assignee: Mostek CorporationInventor: Douglas P. Sheppard
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Patent number: 4389705Abstract: A read only memory (ROM) circuit (10) includes a memory storage transistor (16) which is fabricated to have one of a plurality of threshold voltages corresponding to predetermined data states. The source and drain terminals of the memory transistor (16) are connected between a column node (18) and a bit line (20). A lightly depleted data transfer transistor (30) is connected between the bit line (20) and a data line (14). The column node (18), bit line (20) and data line (14) are precharged. A memory address is decoded to drive a selected word line (12) and a selected column decode line (32) to a high voltage state. A transistor (34) discharges the column node (18). Depending upon the state of the memory storage transistor (16) the bit line (20) is discharged or maintained precharged. The state of bit line (20) is transmitted through the data transfer transistor (30) to the data line (14).Type: GrantFiled: August 21, 1981Date of Patent: June 21, 1983Assignee: Mostek CorporationInventor: Douglas P. Sheppard
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Patent number: 4388705Abstract: A semiconductor memory circuit (10) has a plurality of word lines (12, 14), column lines (16, 18) and bit lines (20, 22). A memory cell transistor (30) has the gate terminal connected to the word line (12) and the drain and source terminals connected between the bit line (20) and the column line (16). A reference transistor (106) is connected to the word line (12) to provide a reference signal for input to a sense amplifier (136). A data line (54) is connected to the bit line (20) to provide the data state from the data storage transistor (30) to the sense amplifier (136). The data bit line (20) and reference bit line (104) are clamped at different pull down voltages. The memory circuit (10) includes a reference circuit that has reference transistor (106) which operates statically to provide a reference signal for the sense amplifier (136).Type: GrantFiled: October 1, 1981Date of Patent: June 14, 1983Assignee: Mostek CorporationInventor: Douglas P. Sheppard
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Patent number: 4388702Abstract: A ROM circuit (10) includes a plurality of multi-bit memory storage transistors (22, 24, 26, 28, 29) and reference transistors (40, 42 and 44) all connected along a word line (16). Each of the storage transistors is provided with bit (18) and column (20) lines for activating a specific memory storage transistor and transmitting the data state thereof to sensing circuitry. A step control signal is transmitted through a control line (80) and applied to a selected one of the memory storage transistors and to each of the reference transistors (40, 42 and 44) on a selected word line (16). The step control signal is sequentially decreased in voltage to apply a progressively increasing gate-to-source voltage to each of the reference transistors (40, 42 and 44) and to a selected one of the memory storage transistors (26). The reference transistors (40, 42, and 44) are sequentially turned on by the increasing gate-to-source bias generated by the step control signal.Type: GrantFiled: August 21, 1981Date of Patent: June 14, 1983Assignee: Mostek CorporationInventor: Douglas P. Sheppard
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Patent number: 4385369Abstract: A semiconductor memory address buffer (10) includes a plurality of serially connected inverter amplifier stages (76, 78, 80, and 82). An output stage (84) is connected to the last two inverter amplifier stages (80, 82). In the active mode of operation circuit (10) functions as a driver which receives an input address signal (A) and produces complementary output address signals (A, A). In a power down mode a group of transistors (18, 20 and 22) are turned off to deactive corresponding stages (76, 78 and 82) to terminate power consumption by these stages. A transistor (36) is activated to drive the input node (38) of a selected stage (80) to turn off a transistor (48) and essentially terminate power consumption by the selected stage (80). The output stage (84) receives differential inputs and functions in a push-pull configuration to produce the complementary output address signals (A, A).Type: GrantFiled: August 21, 1981Date of Patent: May 24, 1983Assignee: Mostek CorporationInventor: Douglas P. Sheppard
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Patent number: RE40423Abstract: A RAM with programmable data port configuration provides for programmable configuration of RAM data ports, and in the case of a multiport RAM, for independent programmable configuration of each data port. A single programmable RAM cell can be utilized in a variety of data port configurations, thereby reducing the number of combinations necessary in a standard cell library or gate array in implement the every possible configuration. In one embodiment of the invention, a dual port RAM is provided with a decoder, an input multiplexer and an output multiplexer for each data port. The input multiplexer for each data port provides several different selectable mappings of a RAM input word of varying sizes to the input bit lines of the respective data port. Similarly, the output multiplexer for each data port provides several different selectable mappings of the RAM output bit lines to the RAM output word.Type: GrantFiled: May 15, 2001Date of Patent: July 8, 2008Assignee: Xilinx, Inc.Inventors: Scott S. Nance, Douglas P. Sheppard, Nicholas J. Sawyer