Abstract: A vector-based Walsh code sequence generator provides for a general architecture that can be easily adapted to any random length sequence and any random number of bits per access. The Walsh code sequence generator can produce a new access on every hardware clock cycle, thereby maximizing the efficiency of the bit sequence requesting process.

Abstract: A vector-based sequence generator (100) provides for a general architecture that can be easily adapted to any random length sequence and any random number of bits per access. The sequence generator (100) can also produce a new access on every hardware clock cycle, thereby maximizing the efficiency of the bit sequence requesting process.

Abstract: A vector-based Walsh code sequence generator (100) provides for a general architecture that can be easily adapted to any random length sequence and any random number of bits per access. The Walsh code sequence generator (100) can produce a new access on every hardware clock cycle, thereby maximizing the efficiency of the bit sequence requesting process.

Abstract: A vector-based sequence generator (100) provides for a general architecture that can be easily adapted to any random length sequence and any random number of bits per access. The sequence generator (100) can also produce a new access on every hardware clock cycle, thereby maximizing the efficiency of the bit sequence requesting process.

Abstract: A bit-serial pipeline Galois Field multiplier for multiplying an element K(X)=K.sub.m-1 X.sup.m-1 +K.sub.m-2 X.sup.m-2 X.sup.m-2 +. . . +K.sub.0 with another element Y(X)=Y.sub.m-1 X.sup.m-1 +Y.sub.m-2 X.sup.m-2 +. . . +Y.sub.0 to obtain Z.sub.0 =Z.sub.m-1 X.sup.m-1 +Z.sub.m-2 X.sup.m-2 +. . . +Z.sub.0, which is also an element of the field generally defined by P(X)=a.sub.m X.sup.m +a.sub.m-1 X.sup.m-1 +a.sub.m-2 X.sup.m-2 +. . . a.sub.1 X+a.sub.0. The multiplier has an input shift register buffer circuit, an intermediate shift register circuit, an output shift register circuit and multiplying and summing device. The input shift register buffer circuit is configured for serially receiving the K(X) coefficients. The multiplying and summing device receives arrangements of K(X) coefficients and the Y(X) coefficients and operates thereon, by multiplying corresponding pairs of register stage elements and Y(X) coefficients and summing the products.