Patents by Inventor Douglas S. Piasecki
Douglas S. Piasecki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10601259Abstract: A current shunt monitor (CSM) circuit for monitoring the current through a sense resistor. An analog circuit provides an analog output signal proportional to the voltage across the sense resistor. A power supply includes a fixed voltage power supply at a first voltage supply level and a floating power supply. The floating power supply operates at a second voltage supply level referenced from the voltage level on a voltage input and a floating ground. The voltage input varies from a voltage level above the first voltage supply level to a voltage level below the first voltage supply level, and the floating power supply provides power to the analog circuit at least when the voltage level of the voltage input is above the first voltage supply level. A crossover circuit switches power from the floating power to the fixed voltage power supply at the first voltage supply level upon detecting the voltage level on the voltage input proximate in value to the first voltage supply level.Type: GrantFiled: December 21, 2018Date of Patent: March 24, 2020Assignee: WiTricity CorporationInventor: Douglas S. Piasecki
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Publication number: 20190123594Abstract: A current shunt monitor (CSM) circuit for monitoring the current through a sense resistor. An analog circuit provides an analog output signal proportional to the voltage across the sense resistor. A power supply includes a fixed voltage power supply at a first voltage supply level and a floating power supply. The floating power supply operates at a second voltage supply level referenced from the voltage level on a voltage input and a floating ground. The voltage input varies from a voltage level above the first voltage supply level to a voltage level below the first voltage supply level, and the floating power supply provides power to the analog circuit at least when the voltage level of the voltage input is above the first voltage supply level. A crossover circuit switches power from the floating power to the fixed voltage power supply at the first voltage supply level upon detecting the voltage level on the voltage input proximate in value to the first voltage supply level.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Inventor: Douglas S. Piasecki
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Patent number: 10164481Abstract: A current shunt monitor (CSM) circuit for monitoring the current through a sense resistor. An analog circuit provides an analog output signal proportional to the voltage across the sense resistor. A power supply includes a fixed voltage power supply at a first voltage supply level and a floating power supply. The floating power supply operates at a second voltage supply level referenced from the voltage level on a voltage input and a floating ground. The voltage input varies from a voltage level above the first voltage supply level to a voltage level below the first voltage supply level, and the floating power supply provides power to the analog circuit at least when the voltage level of the voltage input is above the first voltage supply level. A crossover circuit switches power from the floating power to the fixed voltage power supply at the first voltage supply level upon detecting the voltage level on the voltage input proximate in value to the first voltage supply level.Type: GrantFiled: November 21, 2016Date of Patent: December 25, 2018Assignee: WiTricity CorporationInventor: Douglas S. Piasecki
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Publication number: 20180145543Abstract: A current shunt monitor (CSM) circuit for monitoring the current through a sense resistor. An analog circuit provides an analog output signal proportional to the voltage across the sense resistor. A power supply includes a fixed voltage power supply at a first voltage supply level and a floating power supply. The floating power supply operates at a second voltage supply level referenced from the voltage level on a voltage input and a floating ground. The voltage input varies from a voltage level above the first voltage supply level to a voltage level below the first voltage supply level, and the floating power supply provides power to the analog circuit at least when the voltage level of the voltage input is above the first voltage supply level. A crossover circuit switches power from the floating power to the fixed voltage power supply at the first voltage supply level upon detecting the voltage level on the voltage input proximate in value to the first voltage supply level.Type: ApplicationFiled: November 21, 2016Publication date: May 24, 2018Inventor: Douglas S. Piasecki
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Patent number: 8633844Abstract: In one embodiment, a data acquisition circuit includes an analog multiplexer to receive analog signals and select an analog signal for output, an ADC coupled to the multiplexer to receive the analog signal and perform a conversion of the analog signal to a N-bit digital value in at least N clock cycles, and a controller coupled to the ADC to enable the ADC to compare the analog signal to a second analog signal in a single clock cycle.Type: GrantFiled: January 31, 2012Date of Patent: January 21, 2014Assignee: Silicon Laboratories Inc.Inventor: Douglas S. Piasecki
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Publication number: 20130194121Abstract: In one embodiment, a data acquisition circuit includes an analog multiplexer to receive analog signals and select an analog signal for output, an ADC coupled to the multiplexer to receive the analog signal and perform a conversion of the analog signal to a N-bit digital value in at least N clock cycles, and a controller coupled to the ADC to enable the ADC to compare the analog signal to a second analog signal in a single clock cycle.Type: ApplicationFiled: January 31, 2012Publication date: August 1, 2013Inventor: Douglas S. Piasecki
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Patent number: 8402823Abstract: A metering system can include a pull up circuit to be selectively coupled between a voltage node and a metering line that communicates a signal indicative of status of a flow line through which a metered substance flows. An impedance of the pull up circuit is set to reduce power consumption based on a calibration, and the pull up circuit can be disabled between sampling of the signal to reduce power consumption.Type: GrantFiled: March 31, 2011Date of Patent: March 26, 2013Assignee: Silicon Laboratories Inc.Inventors: Marty Lynn Pflum, Michael L. Duffy, Douglas S. Piasecki, Michael Keith Odland
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Publication number: 20110291678Abstract: A metering system can include a pull up circuit to be selectively coupled between a voltage node and a metering line that communicates a signal indicative of status of a flow line through which a metered substance flows. An impedance of the pull up circuit is set to reduce power consumption based on a calibration, and the pull up circuit can be disabled between sampling of the signal to reduce power consumption.Type: ApplicationFiled: March 31, 2011Publication date: December 1, 2011Inventors: Marty Lynn Pflum, Michael L. Duffy, Douglas S. Piasecki, Michael Keith Odland
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Patent number: 7852061Abstract: An apparatus comprises a band gap voltage generator circuit for generating a band gap voltage. A temperature invariant current generator is located within the band gap voltage generator circuit for generating a temperature invariant current. A temperature invariant current correction circuit is located within the band gap voltage generator circuit and adjusts the output voltage responsive to the temperature invariant current without altering temperature characteristics of the temperature invariant current.Type: GrantFiled: October 1, 2007Date of Patent: December 14, 2010Assignee: Silicon Laboratories Inc.Inventors: Jia-Hau Liu, Alan L. Westwick, Douglas S. Piasecki
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Patent number: 7746262Abstract: A method for coding a digital to analog converter of a successive approximation register analog to digital converter includes the steps of first switching capacitors associated with a bit from ground to a reference voltage. Next, a determination is made of whether a logical value of the bit is a first or a second value. If the logical value is the first value, capacitors associated with a next bit are switched from ground to a reference voltage. If the logical value is the second value, one half of the capacitors associated with the bit currently connected are switched from the reference voltage to ground.Type: GrantFiled: December 19, 2005Date of Patent: June 29, 2010Assignee: Silicon Laboratories Inc.Inventors: Golam R. Chowdhury, Douglas S. Piasecki, Bruce Del Signore, Kevin Kwak
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Patent number: 7660968Abstract: A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks.Type: GrantFiled: June 30, 2007Date of Patent: February 9, 2010Inventors: Donald E. Alfano, Danny J. Allred, Douglas S. Piasecki, Kenneth W. Fernald, Ka Y. Leung, Brian Caloway, Alan Storvik, Paul Highley, Douglas R. Holberg
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Patent number: 7613901Abstract: An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.Type: GrantFiled: March 30, 2007Date of Patent: November 3, 2009Assignee: Silicon Labs CP, Inc.Inventors: Donald E. Alfano, Danny J. Allred, Douglas S. Piasecki, Kenneth W. Fernald, Ka Y. Leung, Brian Caloway, Alvin Storvik, Paul Highley, Douglas R. Holberg
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Publication number: 20090085651Abstract: An apparatus comprises a band gap voltage generator circuit for generating a band gap voltage. A temperature invariant current generator is located within the band gap voltage generator circuit for generating a temperature invariant current. A temperature invariant current correction circuit is located within the band gap voltage generator circuit and adjusts the output voltage responsive to the temperature invariant current without altering temperature characteristics of the temperature invariant current.Type: ApplicationFiled: October 1, 2007Publication date: April 2, 2009Applicant: SILICON LABORATORIES INC.Inventors: JIA-HAU LIU, ALAN L. WESTWICK, DOUGLAS S. PIASECKI
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Patent number: 7504900Abstract: An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.Type: GrantFiled: March 30, 2007Date of Patent: March 17, 2009Assignee: Silicon Labs CP, Inc.Inventors: Donald E. Alfano, Danny J. Allred, Douglas S. Piasecki, Kenneth W. Fernald, Ka Y. Leung, Brian Caloway, Alan Storvik, Paul Highley, Douglas R. Holberg
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Patent number: 7498962Abstract: A method for converting analog data to digital data includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.Type: GrantFiled: December 29, 2006Date of Patent: March 3, 2009Assignee: Silicon Labs CP, Inc.Inventors: Donald E. Alfano, Danny J. Allred, Douglas S. Piasecki, Kenneth W. Fernald, Ka Y. Leung, Brian Caloway, Alvin Storvik, Paul Highley, Douglas R. Holberg
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Patent number: 7411538Abstract: A circuit includes a successive approximation register A/D converter for performing analog to digital conversions. The register has a ground pin and a ground sense pin. The ground sense pin is connected to a ground port of the circuit. A multiplexer connects the ground sense pin of the successive approximation register A/D converter to one of a plurality of I/O ports of the circuit package. A switch selectively connects the ground sense pin of the successive approximation register A/D converter to the ground port.Type: GrantFiled: March 31, 2007Date of Patent: August 12, 2008Assignee: Silicon Laboratories Inc.Inventor: Douglas S. Piasecki
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Publication number: 20070139243Abstract: A method for coding a digital to analog converter of a successive approximation register analog to digital converter includes the steps of first switching capacitors associated with a bit from ground to a reference voltage. Next, a determination is made of whether a logical value of the bit is a first or a second value. If the logical value is the first value, capacitors associated with a next bit are switched from ground to a reference voltage. If the logical value is the second value, one half of the capacitors associated with the bit currently connected are switched from the reference voltage to ground.Type: ApplicationFiled: December 19, 2005Publication date: June 21, 2007Applicant: SILICON LABORATORIES, INC.Inventors: Golam R. Chowdhury, Douglas S. Piasecki, Kevin Kwak, Bruce Del Signore
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Patent number: 7171542Abstract: A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.Type: GrantFiled: June 19, 2001Date of Patent: January 30, 2007Assignee: Silicon Labs CP, Inc.Inventors: Donald E. Alfano, Danny Allred, Douglas S. Piasecki, Kenneth W. Fernald, Ka Y Leung, Brian Caloway, Alvin Storvik, Paul Highley, Douglas R Holberg
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Patent number: 7126206Abstract: A capacitor structure in an integrated circuit includes a capacitor region defined within the boundaries thereof with an active circuit layer formed on the surface of the semiconductor substrate. A planarization layer is disposed over the active circuit layer and electrically isolated therefrom in at least the capacitor region. A metal capacitor layer is formed over the planarization layer within the capacitor region and having the bottom plates of a plurality of capacitors defined therein. A layer of dielectric is formed on the bottom plates of the plurality of capacitors of a predetermined thickness. A top plate is formed on the dielectric for each of the plurality of capacitors to define each of the plurality of capacitors, such that a portion of each of the bottom plates extends outside of the boundaries of the associated top plate.Type: GrantFiled: December 30, 2004Date of Patent: October 24, 2006Assignee: Silicon Labs CP, Inc.Inventor: Douglas S. Piasecki
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Patent number: 7046035Abstract: A pin interface for an integrated circuit. The pin interface includes logic gates for processing digital signals, and analog lines for carrying analog signals. The pin interface includes circuits for disabling the digital circuits when configured to carry analog signals. A comparator is associated with at least one of the pins for comparing the analog voltage level thereon with a reference voltage.Type: GrantFiled: April 26, 2005Date of Patent: May 16, 2006Assignee: Silicon Laboratories CP, Inc.Inventors: Douglas S. Piasecki, Alvin C. Storvik, II