Abstract: A method and apparatus for correcting the duty cycle of an uncorrected differential clock signal having a sinusoidal characteristic and outputting a corrected differential square wave clock signal. In the method, the uncorrected differential clock signal is provided as an uncorrected differential current to a pair of summing nodes. A correction differential voltage is generated as a signal corresponding to the inverse of the corrected differential clock signal and having a common mode voltage of one of the correction differential signals relative to a common mode voltage of the other of the correction differential voltages that depends on the duty cycle of the uncorrected differential clock signal. A correction differential current is generated, corresponding to the correction differential voltage.

Abstract: The duty cycle for a periodic signal such as a clock signal is idealized by feeding back duty cycle information. Duty cycle information is detected by a capacitor connected in serial with a resistor across the outputs of a feedback differential transistor pair. Over time, the capacitor will be charged or discharged when the duty cycle varies from fifty percent. The detected duty cycle information is fed back to an amplifier where the incoming clock signal is mixed with the feedback signal. The amplifier itself comprises a first differential comparator stage receiving the uncorrected clock signal, a gain stage that amplifies and level shifts the feedback signal, and a second differential pair receiving the amplified feedback signal.

Abstract: In systems requiring the alignment of two clock signals or the alignment of a clock signal to a serial data stream, a current mode interpolator is often used to position the output clock signal. Traditional scan tests using external pins of the device are inappropriate because of their timing penalty and other built in self tests are inappropriate because of a large area or circuit complexity penalty. Therefore, a built in self test has been developed that does not impact the normal performance of the device and requires minimal additional circuitry. In this method, a small digital state machine is utilized to force the digital control logic for the current mode interpolator such that a single bit current comparator is sufficient to detect defects in the digital control logic and the current mode interpolator.