Abstract: A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit configured to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator configured to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

Abstract: A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

Abstract: A method and apparatus for buffering a signal in a voltage island that is in standby or sleep mode. The apparatus uses a buffer(s) that are powered from a global power supply voltage that is always powered, and such buffer(s) are placed within the sleeping island itself. The sleeping island can be at the same or different voltage from the global voltage.

Abstract: A metal oxide semiconductor transistor having a slew-rate control is disclosed. The transistor having a slew-rate control includes an elongated diffusion area and an elongated gate overlying the diffusion area. The elongated diffusion area has at least two diffusion regions, each having a threshold voltage that is different from each other. The elongated gate has a gate contact at only one side of the elongated diffusion area.

Abstract: A method and apparatus for buffering a signal in a voltage island that is in standby or sleep mode. The apparatus uses a buffer(s) that are powered from a global power supply voltage that is always powered, and such buffer(s) are placed within the sleeping island itself. The sleeping island can be at the same or different voltage from the global voltage.

Abstract: The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

Abstract: The protection circuit of the present invention addresses the problem of indeterminate logic levels caused by loss of one of the power supplies in a two-power-supply CMOS integrated circuit. The circuit of the present invention replaces the typical scheme of power supply sequencing to fix the problem. The circuit disclosed herein detects the state of the core voltage and disables the output drivers when the core voltage is detected as being off. The disabled drivers are put into a high impedance state, thereby eliminating the potential for damage and eliminating the need for power supply sequencing. The invention also protects against the sudden loss of the integrated circuit core voltage, VDD, power supply during normal operation.

Abstract: A metal oxide semiconductor transistor having a slew-rate control is disclosed. The transistor having a slew-rate control includes an elongated diffusion area and an elongated gate overlying the diffusion area. The elongated diffusion area has at least two diffusion regions, each having a threshold voltage that is different from each other. The elongated gate has a gate contact at only one side of the elongated diffusion area.

Abstract: A pre-driver circuit in an I/O circuit for an integrated circuit performs the combined functions of voltage level shifting, slew rate control, and tri-state capability, in a single circuit to avoid additional delay caused by implementing any combination of these functions in two or more circuits.

Abstract: A level shifting driver shifts a low magnitude logic signal to a high magnitude logic signal while preventing a high supply voltage as associated with the high magnitude logic signal from feeding back into logic devices associated with providing the low magnitude logic signal. An input terminal receives the low magnitude logic signal from a given low voltage logic device. An N-channel MOSFET has its channel disposed serially between the input terminal and an output terminal and its gate coupled to a low supply voltage of the low voltage logic device. A latch network biased by the high supply voltage has one node of its latch coupled to the output terminal for providing an output signal representative of the low magnitude logic signal but of a high magnitude established in accordance with the high supply voltage.

Abstract: A level shifting driver shifts a low magnitude logic signal to a high magnitude logic signal while preventing a high supply voltage as associated with the high magnitude logic signal from feeding back into logic devices associated with providing the low magnitude logic signal. An input terminal receives the low magnitude logic signal from a given low voltage logic device. An N-channel MOSFET has its channel disposed serially between the input terminal and an output terminal and its gate coupled to a low supply voltage of the low voltage logic device. A latch network biased by the high supply voltage has one node of its latch coupled to the output terminal for providing an output signal representative of the low magnitude logic signal but of a high magnitude established in accordance with the high supply voltage.