Patents by Inventor Doyle W. Rivers
Doyle W. Rivers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11928330Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.Type: GrantFiled: November 3, 2021Date of Patent: March 12, 2024Assignee: Micron Technology, Inc.Inventors: Shekoufeh Qawami, Doyle W. Rivers
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Publication number: 20220057939Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.Type: ApplicationFiled: November 3, 2021Publication date: February 24, 2022Inventors: Shekoufeh Qawami, Doyle W. Rivers
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Patent number: 11194472Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.Type: GrantFiled: April 14, 2020Date of Patent: December 7, 2021Assignee: Micron Technology, Inc.Inventors: Shekoufeh Qawami, Doyle W. Rivers
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Publication number: 20200241751Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.Type: ApplicationFiled: April 14, 2020Publication date: July 30, 2020Inventors: Shekoufeh Qawami, Doyle W. Rivers
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Patent number: 10649656Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.Type: GrantFiled: December 28, 2017Date of Patent: May 12, 2020Assignee: Micron Technology, Inc.Inventors: Shekoufeh Qawami, Doyle W. Rivers
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Publication number: 20190205030Abstract: Techniques to update a trim parameter in non-volatile memory during either a manufacturing stage or a post-manufacturing stage are described. Trim parameters may be stored in a register located within the memory device that is inaccessible by a host device during a normal mode of operation. Post-manufacturing updates to trim parameters by the host device may be feasible by creating registers located within the memory device that are accessible to the host device to provide information regarding trim parameter setting updates. The memory device may read the information from the registers accessible to the host device to update trim parameters stored in the register inaccessible by the host device. In this manner, the host device may not have a direct access to the trim parameters but still be able to provide an update to the trim parameters by updating an entry of the registers accessible by the host device.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Inventors: Shekoufeh Qawami, Doyle W. Rivers
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Patent number: 9298545Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location of the second memory block can be different than the first location of the first memory block.Type: GrantFiled: April 17, 2014Date of Patent: March 29, 2016Assignee: Micron Technology, Inc.Inventors: Sampath K. Ratnam, Troy D. Larsen, Doyle W. Rivers, Troy A. Manning, Martin L. Culley
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Publication number: 20140325316Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks.Type: ApplicationFiled: April 17, 2014Publication date: October 30, 2014Applicant: Micron Technology, Inc.Inventors: Sampath K. Ratnam, Troy D. Larsen, Doyle W. Rivers, Troy A. Manning, Martin L. Culley
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Patent number: 8732557Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first memory block and writing a second portion of the codeword in a second memory block. The first memory block and the second memory block can be different memory blocks. The first portion of the codeword can be written in a different location in the first memory block than the second portion of the codeword is written in the second memory block.Type: GrantFiled: May 31, 2011Date of Patent: May 20, 2014Assignee: Micron Technology, Inc.Inventors: Sampath K. Ratnam, Troy D. Larsen, Doyle W. Rivers, Troy A. Manning, Martin L. Culley
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Publication number: 20120311406Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Sampath K. Ratnam, Troy D. Larsen, Doyle W. Rivers, Troy A. Manning, Martin L. Culley